3D SRAM Bit Cell Structure for Threshold Match and Leakage Control
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Solution Overview
Problem
Static random access memory (SRAM) bit cells face issues with threshold voltage mismatch and isolation leakage, particularly at low minimum operating voltages and lower power operation, due to asymmetric variations in well doping caused by random dopant fluctuation.
Innovation Solution
The solution involves forming SRAM bit cells with field-effect transistors on separate substrates, where the transistors are fabricated in the same well and connected using face-to-face metal feature bonding, reducing threshold voltage mismatch and isolation leakage by eliminating the need for separate wells of opposite conductivity type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are fabricated in separate wells of opposite conductivity type, then device functionality is achieved, but threshold voltage mismatch occurs due to random dopant fluctuation
Solution Approach 1:
The patent merges the NMOS and PMOS transistor fabrication into a single shared well structure, eliminating the need for separate wells of opposite conductivity types. This combining approach reduces the sources of variation and achieves better threshold voltage matching between transistors while simplifying the overall device structure.
Solution Approach 2:
The patent changes the fundamental parameter of well structure from separate opposite-type wells to a single shared well. This parameter change fundamentally alters the doping configuration and eliminates random dopant fluctuation effects that cause threshold voltage mismatch in conventional separate-well structures.
2Reliability
If transistors are fabricated in separate wells, then device functionality is achieved, but isolation leakage occurs
Solution Approach 1:
By merging the NMOS and PMOS transistors into a single shared well, the patent eliminates the interfaces between separate wells that serve as leakage paths. The unified well structure removes these isolation boundaries, thereby reducing isolation leakage while maintaining proper device functionality.
3Manufacturing precision
If three-dimensional integration with face-to-face metal bonding is used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional integration to three-dimensional integration by stacking substrates and forming face-to-face metal bonds between upper and lower substrates. This dimensional change enables precise alignment and bonding of metal features while achieving complex interconnect structures that improve manufacturing precision through controlled vertical stacking.
Data Source
AI summary
Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.