3D Semiconductor Stack Layout for Dense Connection Regions
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of forming fine patterns, which restricts their performance and manufacturing efficiency.
Innovation Solution
A three-dimensional semiconductor device architecture is developed, featuring vertically stacked stacks with alternating electrodes and insulating layers, and a stepwise structure in the connection region to enhance integration density, allowing for better filling of insulation layers and improved contact plug connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor devices are used, then manufacturing processes are simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar structures to three-dimensional vertically stacked structures. Multiple electrode layers and insulating layers are stacked vertically to form memory cells in the third dimension, thereby increasing integration density without requiring finer lateral patterning. The stack structure includes alternating electrode layers and insulating layers extending vertically from the substrate, enabling higher capacity per unit area.
2Manufacturing precision
If fine patterns are formed to increase integration density, then more memory cells fit in the same area, but extremely high-priced apparatuses are needed
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning which requires expensive equipment, the patent stacks multiple electrode and insulating layers vertically. This approach achieves higher density by utilizing the vertical dimension, allowing standard patterning equipment to be used while still attaining greater memory cell capacity per unit area.
Solution Approach 2:
The memory device is divided into multiple discrete layers including first electrode layers, second electrode layers, and insulating layers stacked vertically. Each layer can be formed and patterned separately using standard processes, avoiding the need for single-step fine patterning of the entire memory cell structure. This segmentation enables modular manufacturing with conventional equipment.
3Area of stationary object
If stacks extend far into the connection region, then more connection area is available, but insulation layer filling becomes less efficient
Solution Approach 1:
The stack structure implements asymmetric electrode widths at different heights. The first electrode layers have a first width in the connection region, while the second electrode layers have a second width that is greater than the first width. This asymmetric configuration optimizes both connection area availability and insulation layer filling efficiency by providing wider support surfaces for insulating layers while maintaining adequate connection region footprint.
Data Source
AI summary
A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.