3D Memory Stack Contacts for Dense Arrays and Fewer Word-Line Drivers
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Solution Overview
Problem
Planar memory cells face density limitations and fabrication challenges as feature sizes approach a lower limit, leading to increased complexity and cost in manufacturing.
Innovation Solution
A 3D memory architecture with interleaved conductive and dielectric layers and innovative contact structures that extend through multiple memory stacks, connecting to specific word/gate lines, reducing the need for word line string drivers and simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density increases, but fabrication complexity and cost increase significantly as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Multiple memory stacks are formed vertically, with contact structures extending through multiple stacks to connect word lines across different levels. This vertical stacking enables higher memory density without requiring further scaling of planar feature sizes, thereby avoiding the fabrication complexity and cost associated with advanced lithography processes.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but manufacturing cost increases due to challenging and costly process technology
Solution Approach 1:
By stacking multiple memory structures vertically in the third dimension, the patent achieves higher memory density using existing planar fabrication processes. The contact structures that extend through multiple stacks can be formed using standard via and fill processes, avoiding the need for costly advanced lithography tools required for further planar scaling.
3Quantity of substance
If 3D memory architecture is implemented with multiple stacks, then memory density increases, but device complexity increases due to additional contact structures and interconnections
Solution Approach 1:
The contact structures extending through multiple memory stacks serve multiple functions: they provide electrical connections for word lines across different stack levels, enable shared control signals, and reduce the overall number of separate interconnection structures needed. This multi-functionality approach manages structural complexity by having single structures perform multiple roles.
Solution Approach 2:
The patent combines multiple word line connections into single contact structures that traverse through multiple stacks. Instead of having separate contacts for each stack level, the same contact structure serves multiple stacks, thereby reducing the total number of interconnection elements and managing structural complexity.
4Ease of manufacture
If contact structures extend through multiple stack structures, then word line driver usage is optimized and fabrication is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The contact structures are formed to extend through multiple stacks in advance, before final interconnection steps. This preliminary formation establishes the vertical pathways early in the fabrication sequence, allowing subsequent layers to be built around these pre-defined structures. This approach simplifies later fabrication steps while managing alignment requirements through process sequencing.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first stack structure including interleaved conductive layers and dielectric layers, a second stack structure over the first stack structure in a first direction and including interleaved conductive layers and dielectric layers, and a contact structure extending through the first stack structure and the second stack structure in the first direction and in contact with a first conductive layer of the conductive layers in the first stack structure and a second conductive layer of the conductive layers in the second stack structure.