3D Semiconductor Stack With Single-Crystal Channels and Dense Vias
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in Through-Silicon Via (TSV) density, alignment issues, and the need for high-temperature processing, which affects the reliability of interconnects and transistor performance.
Innovation Solution
The development of a 3D semiconductor device with multiple metal layers and single crystal silicon layers, where transistors with single crystal channels are aligned with less than 40 nm error, and via diameters are less than 500 nm, enabling high-density interconnections and reduced temperature processing through layer transfer techniques like Smart Stacking and ion-cut methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through-Silicon Via (TSV) technology is used for 3D IC interconnections, then vertical connectivity between stacked chips is achieved, but TSV density is limited due to large landing pad requirements and alignment issues
Solution Approach 1:
The patent transitions from planar 2D interconnections to three-dimensional stacked architecture with vertical interlayer via connections, enabling higher interconnect density by utilizing the vertical dimension for signal routing between multiple chip layers
Solution Approach 2:
The patent divides the interconnection system into separate components: through-silicon vias for vertical penetration, landing pads for electrical contact, and interlayer via connections for horizontal routing, allowing each component to be optimized independently for density and alignment tolerance
2Speed
If device scaling is continued to reduce size, then device speed and area cost are improved, but interconnection wiring dominance increases performance limitations
Solution Approach 1:
The patent moves interconnections from planar routing to three-dimensional vertical routing through stacked chip architecture, shortening interconnect lengths and reducing the number of wiring layers required, thereby decreasing interconnection complexity and its dominance over device performance
3Quantity of substance
If via diameters are reduced to increase density, then interconnect density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces horizontal interlayer via connections as a separate routing dimension, allowing small vertical through-silicon vias to be precisely aligned with larger horizontal interlayer via connections, thereby increasing overall via density while maintaining manufacturable alignment tolerances through the additional spatial dimension
Data Source
AI summary
A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.