3D Semiconductor Stack Structure With Dummy Channel Plugs Against Warpage
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the planar type memory cells, and there is a need for improved reliability and structure in three-dimensional semiconductor devices to address issues such as warpage, deformation, and pattern abnormalities.
Innovation Solution
A three-dimensional semiconductor device is designed with stack structures of conductive and insulation layers, channel plugs, and dummy channel plugs, where the dummy channel plugs are strategically placed to support the edge channel plugs and the slit structure, using materials like nitride and oxide to enhance structural integrity and prevent warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are used to achieve high integration degree, then the occupying area is reduced, but the integration degree reaches a limit and operation reliability deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked structure, where multiple memory cell layers are vertically stacked above each other. This dimensional change enables continued scaling and integration density improvement while maintaining operation reliability through the symmetric and balanced three-dimensional architecture.
2Quantity of substance
If three-dimensional stacked structures are formed to improve integration degree, then the occupying area is reduced, but warpage and deformation occur
Solution Approach 1:
The patent introduces dummy channel plugs adjacent to the slit structure that do not extend through the entire thickness of the stack structure, creating an asymmetric configuration that counterbalances the warpage and deformation forces generated by the slit structure and edge channel plugs. This anti-weight approach compensates for structural instability while maintaining high integration density.
Solution Approach 2:
The patent employs asymmetric design where dummy channel plugs are positioned only on one side of the slit structure and have different lengths compared to edge channel plugs. This asymmetric configuration creates counterbalancing stresses that prevent warpage and deformation in the three-dimensional stacked structure, resolving the structural stability issue.
3Stability of the object's composition
If dummy channel plugs are added to prevent warpage, then structural stability is improved, but device complexity increases
Solution Approach 1:
The patent incorporates dummy channel plugs during the initial formation process of the three-dimensional stacked structure, before the slit structure is created. By pre-positioning these structural support elements, the patent prevents warpage and deformation from occurring during subsequent processing steps, thereby improving structural stability without significantly increasing overall device complexity.
Data Source
AI summary
A three-dimensional (3D) semiconductor device includes a plurality of stack structures, a plurality of channel plugs, a slit structure and a plurality of dummy channel plugs. The stack structures include at least two conductive layers and at least two insulation layers, each being alternately stacked. The channel plugs are vertically formed through the stack structure. The slit structure is arranged at one side of the stack structure. The plurality of dummy channel plugs is arranged in the stack structures to be adjacent to the slit structure. Each of the channel plugs includes a channel insulation layer and a channel layer. Each of the dummy channel plugs includes at least one of the channel insulation layer, the channel layer, and a material of the plurality of conductive layers.