3D Integrated Circuit Stack with Dummy Die for Warpage Control

The patent applies local quality by introducing a dummy die with specific material properties and thickness at a particular location (adjacent to the device die) to locally compensate for CTE mismatch. The dummy die has a thickness between 50-200 micrometers and is made of a material with CTE matched to the device die, creating a localized correction that addresses the warpage issue without affecting the overall 3DIC stacking architecture.

The patent employs asymmetry by placing a dummy die of asymmetric thickness (50-200 micrometers) adjacent to the device die in the stack. This asymmetric configuration creates a compensatory effect where the dummy die's different thickness and material properties balance out the CTE mismatch caused by the device die, thereby reducing package warpage while maintaining the asymmetric stacking architecture.

The patent applies preliminary action by forming through substrate vias and bonding structures on the dummy die simultaneously with the device die during the same bonding process. The through substrate vias are pre-formed in the dummy die before stacking, and the bonding structures are prepared in advance, allowing both dies to be bonded in a single hybrid bonding step without requiring additional post-bonding processing steps.

The dummy die serves multiple functions simultaneously: it provides CTE compensation, acts as a mechanical support structure, and contains through substrate vias for electrical connectivity. This multi-functional design allows the dummy die to service multiple purposes, reducing the need for separate components and simplifying the overall manufacturing process despite the added complexity of through substrate vias.