3D Stack FET Layout Using In-Situ FinFET and GAAFET Integration
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Solution Overview
Problem
Current methods for manufacturing three-dimensional stack field-effect transistors (3DS FETs) face challenges such as high costs and complexity, particularly due to thermal budget constraints and poor controllability in sequential 3D integration, and incompatibility with existing GAAFET processes in self-aligned monolithic 3D integration.
Innovation Solution
A novel 3DS FET is developed with a lower fin field-effect transistor (FinFET) device formed in situ using a sub-fin region, integrated with an upper GAAFET device, reducing manufacturing complexity and improving controllability through modified processes, including the use of sacrificial layers and nanosheets, patterning, and etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sequential 3D integration is used, then the process is simple, but it requires two times of processes resulting in higher costs and upper layer devices facing integration thermal budget constraints
Solution Approach 1:
The patent merges the formation of lower FinFET and upper GAAFET devices into a single integrated process flow. The common process steps include: forming a stack of sacrificial layers and nanosheets, patterning into stripe shape, thinning the fin, forming isolation layer, etching to expose fin, forming dummy gate, etching stack and fin, forming lower source/drain portions, forming source/drain inter isolation layer, forming upper source/drain portions, and replacing dummy gate with gate stack. This unified approach eliminates the need for separate process sequences while maintaining manufacturing simplicity.
2Productivity
If self-aligned monolithic 3D integration is used, then it is highly integrated and superior in performance, but the process is complex and not very compatible with existing GAAFET processes, requiring significant increase in process steps
Solution Approach 1:
The patent creates a universal process that can manufacture both FinFET and GAAFET devices using the same sequence of steps and equipment. The process is designed to be compatible with existing GAAFET fabrication capabilities while also producing FinFET structures. Key universal elements include the stack formation method, patterning approach, thinning process, isolation layer formation, and gate stack replacement, all of which work for both device types without requiring additional specialized process steps.
Solution Approach 2:
The patent performs preliminary actions by forming the complete stack of sacrificial layers and nanosheets before any device-specific processing occurs. The dummy gate is formed early in the process before the final gate stack is created. These preliminary structures serve multiple purposes: they define the future device geometry, provide alignment references for subsequent steps, and enable both FinFET and GAAFET configurations to be achieved from the same starting point.
Data Source
AI summary
Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.