3D Semiconductor Assembly Heat Sink Structure for Central Stack Cooling
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Solution Overview
Problem
Current package-level heat dissipation techniques for 3D stacked chip packages, such as those incorporating high bandwidth memory (HBM), are insufficient for effectively dissipating heat from densely stacked chips in the central region, with existing methods like thermal interface materials and increased micro bumps being ineffective.
Innovation Solution
A semiconductor assembly with a heat sink structure that includes a first semiconductor wafer, a memory stack, and a second semiconductor wafer, where the second wafer has a heat sink structure configured to dissipate heat through thermal conductive paths formed within the assembly, utilizing silicon substrates and heat dissipating components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thermal interface materials and cavities between dies are used, then heat dissipation is improved, but heat dissipation from the central region of densely stacked chips remains insufficient
Solution Approach 1:
The patent transitions from planar heat dissipation at the package level to three-dimensional heat dissipation by forming thermal conductive paths through the vertical stack of chips. Through-silicon vias (TSVs) and embedded heat dissipation structures create conductive pathways in the depth dimension, allowing heat to be conducted from the central regions of stacked chips to heat sink structures, thereby resolving the insufficiency of conventional package-level techniques.
Solution Approach 2:
The patent introduces thermal conductive materials and heat dissipation structures as intermediary elements between the heat-generating chip regions and the external environment. These intermediaries include thermal conductive paths formed through the chips, heat dissipation structures embedded within the stack, and heat sink structures that collectively transfer heat from the central regions where conventional methods fail.
2Temperature
If the number of micro bumps is increased, then heat dissipation is improved, but heat dissipation from densely stacked chips in the central region remains ineffective
Solution Approach 1:
The patent extracts the heat dissipation function from the peripheral micro bump structures and relocates it to embedded heat dissipation structures within the central regions of the chips. By removing the reliance on increased micro bump numbers and implementing internal thermal management structures, the solution reduces device complexity while effectively addressing central region heat dissipation.
3Quantity of substance
If 3D stacked chip packages are used, then integration density is improved, but heat dissipation from densely stacked chips becomes challenging
Solution Approach 1:
The patent implements nested heat dissipation structures within the 3D stacked chip architecture. Thermal conductive paths are formed through the chips, with heat dissipation structures embedded within the stack, and heat sink structures positioned to receive heat from multiple levels. This nested arrangement enables effective heat dissipation while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The heat sink structure effectively dissipates heat generated by the semiconductor assembly through thermal conductive paths, improving heat management in 3D stacked chip packages.
Implementation Method 1
a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack through a first thermal conductive path and a second thermal conductive path within the semiconductor assembly
Data Source
AI summary
A semiconductor assembly is provided, which includes a first semiconductor wafer, a memory stack, and a second semiconductor wafer. The memory stack is bonded to the first semiconductor wafer, and the second semiconductor wafer is bonded to the memory stack. The second semiconductor wafer includes a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack through a first thermal conductive path and a second thermal conductive path within the semiconductor assembly.