3D Stack Memory Word Line Decoding
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Solution Overview
Problem
Highly integrated semiconductor memory devices with two-dimensional structures are approaching limitations, necessitating the development of three-dimensional structures with efficient word line decoding methods to enhance integration and performance.
Innovation Solution
A resistance semiconductor memory device with a three-dimensional stack structure, featuring alternately disposed word line and bit line layers, memory cell layers, and a decoding system that includes vertical, main, and section decoders to select and operate sub-word lines, allowing for efficient word line decoding and high integration capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory cell structures are used to achieve simple decoding, then device complexity is reduced, but integration density and capacity are limited
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory cell stacking, arranging memory cells vertically across multiple layers. This dimensional change enables higher integration density without proportionally increasing decoding complexity, as the stacking architecture allows shared word lines and bit lines to serve multiple layers simultaneously.
Solution Approach 2:
The patent divides the memory device into multiple stacked layers, each containing memory cells, word lines, and bit lines. This segmentation allows independent addressing and decoding of specific layers while maintaining overall system integration, resolving the contradiction between complexity and density by managing each segment separately.
2Quantity of substance
If three-dimensional stack structures are implemented to increase integration density, then capacity is improved, but word line decoding complexity increases
Solution Approach 1:
The patent implements shared word lines and bit lines that serve multiple memory cell layers simultaneously. A single word line can activate memory cells across several stacked layers, reducing the total number of word lines required and simplifying the decoding logic despite the increased integration density.
Solution Approach 2:
The patent introduces intermediate selection mechanisms, including select transistors and control gates, that mediate between the address decoder and the memory cells. These intermediaries manage the complexity of three-dimensional addressing by providing structured control over which cells are accessed in which layers, making the decoding process more manageable.
3Quantity of substance
If more word lines are added to address additional memory layers, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the functions of multiple word lines and bit lines by having them share common physical structures across stacked layers. Instead of providing completely separate wiring for each layer, the same word lines and bit lines are extended vertically to serve multiple layers, reducing the total number of distinct conductors and easing alignment requirements.
Solution Approach 2:
The patent employs a nested architecture where memory cell layers are stacked within a common structure, with word lines and bit lines forming a hierarchical arrangement. The shared conductors are positioned to intersect with multiple layers in a systematic pattern, allowing precise addressing through combinatorial selection while maintaining manufacturable alignment tolerances.
Data Source
AI summary
A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.