3D Stack Package Power Delivery via Parasitic Capacitors
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Solution Overview
Problem
The existing 3D stack package semiconductor integrated circuits face challenges in reducing size while maintaining stable power delivery, as the increase in through chip vias leads to larger chip sizes and instability in power supply, affecting operational reliability.
Innovation Solution
The integration of parasitic capacitors formed between low voltage and high voltage lines, along with doping regions, serves as reservoir capacitors to stabilize power delivery and reduce the number of active layer capacitors, thereby minimizing chip size and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of through chip vias is increased to improve power delivery, then power supply stability is improved, but chip size increases
Solution Approach 1:
The patent transitions from planar capacitor placement to three-dimensional stacking, where reservoir capacitors are formed in vertical layers between different voltage lines (HV and LV) through the chip thickness. This vertical dimension allows capacitor integration without increasing chip footprint, resolving the contradiction between power stability and chip size.
Solution Approach 2:
The patent changes the physical state and configuration of capacitors from traditional planar devices to vertically stacked reservoir capacitors formed by doping regions extending through the chip. This parameter change in capacitor architecture enables higher capacitance density per unit area, improving power stability without proportionally increasing chip area.
2Reliability
If the number of through chip vias is increased to improve power delivery, then power supply stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the functions of through chip vias and reservoir capacitors into a single integrated structure. The doping regions that form reservoir capacitors also serve as the via structures, combining two previously separate manufacturing processes into one, thereby reducing manufacturing complexity while maintaining power stability.
Solution Approach 2:
The doping regions perform multiple functions simultaneously: they act as reservoir capacitors for power stability, serve as through chip vias for electrical connection, and provide isolation between different voltage domains. This multi-functionality reduces the overall device complexity by eliminating redundant structures.
3Reliability
If reservoir capacitors are formed between HV and LV lines to stabilize power, then power supply stability is improved, but isolation between voltage lines becomes more challenging
Solution Approach 1:
The patent introduces an intermediary material filling the spaces between adjacent doping regions that form reservoir capacitors. This intermediary material provides electrical isolation between high voltage and low voltage lines while allowing the capacitive function to operate, solving the isolation challenge created by vertical capacitor stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides stable power supply, reduces chip size, and reinforces the power mesh, making the semiconductor integrated circuit robust against noise and improving operational reliability.
Implementation Method 1
The integration of parasitic capacitors formed between low voltage and high voltage lines, along with doping regions, serves as reservoir capacitors to stabilize power delivery
Implementation Method 2
along with doping regions, serves as reservoir capacitors to stabilize power delivery
Data Source
AI summary
An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other. An isolation layer is inserted between the first conductive line and the second conductive line.