3D Stack Package Power Mesh via Horizontal Coupling
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Solution Overview
Problem
Conventional semiconductor integrated circuits face issues with unstable power supply and signal transmission due to ohmic drop in vertically stacked through-chip vias, leading to potential malfunctions and reduced high-speed operation performance, especially as the number of stacked chips increases.
Innovation Solution
The implementation of a horizontal common conductive layer that couples vertically formed through-chip vias, creating a power supply mesh structure to reduce resistance and stabilize power distribution, along with additional conductive layers and coupling pads for signal monitoring and error analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked through-chip vias are used to interface power supplies in a 3D stack package, then the memory capacity and packaging density are increased, but ohmic drop occurs in the vertical vias leading to unstable power supply and signal transmission
Solution Approach 1:
The patent introduces a horizontal dimension to the power distribution network by adding a common conductive layer that couples through-chip vias horizontally. This creates a two-dimensional mesh structure (vertical vias + horizontal coupling) that reduces reliance on single vertical paths, thereby mitigating ohmic drop effects while maintaining the vertical stacking architecture for high density.
Solution Approach 2:
The patent merges multiple through-chip vias into a common power network by introducing a common conductive layer that electrically couples them together. This creates a unified power distribution mesh where multiple vias work in parallel, reducing overall resistance and improving power supply stability without sacrificing the high-density vertical stacking.
2Productivity
If the number of stacked semiconductor chips is increased to enhance memory capacity, then packaging density improves, but the number of through-chip vias increases leading to greater ohmic drop and potential malfunctions
Solution Approach 1:
By adding horizontal coupling layers between vertically stacked chips, the patent creates a multi-dimensional power and signal distribution network. This allows signals and power to reach upper chips through multiple parallel paths (direct vertical paths + horizontal coupling paths), reducing the impact of ohmic drop as the number of stacked chips increases.
Solution Approach 2:
The common conductive layer is formed in advance during the packaging process to pre-establish low-resistance coupling paths between through-chip vias. This preliminary action ensures that when multiple chips are stacked, the power distribution network is already optimized to handle the increased number of vias and reduce cumulative ohmic drop effects.
3Ease of manufacture
If conventional vertical through-chip via structure is used, then manufacturing is simplified, but power supply instability and signal transmission issues occur due to ohmic drop
Solution Approach 1:
The patent combines the simple vertical via formation process with an additional horizontal coupling step. The common conductive layer is formed using standard semiconductor fabrication techniques (deposition and patterning) that are compatible with existing manufacturing processes, thereby maintaining ease of manufacture while significantly improving power distribution stability through the merged vertical-horizontal mesh structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively stabilizes power supply, reduces the risk of malfunctions, and enables precise signal transfer analysis, ensuring reliable high-speed operation without increasing chip size, while allowing for early detection of potential signal transfer failures.
Implementation Method 1
a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction
Data Source
AI summary
A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.