3D Semiconductor Metal Layer Stack With Thermal Vias for Heat Removal
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Solution Overview
Problem
The challenge of heat removal in 3D stacked integrated circuits and chips is significant due to high power density and thermal resistance, which affects the performance and efficiency of these devices.
Innovation Solution
The implementation of a 3D semiconductor device with precise alignment and bonding of metal layers, including global and local power distribution networks, and the use of hybrid bonding and heat removal paths to efficiently dissipate heat from the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3D stacking of semiconductor devices is implemented to reduce wire lengths, then wiring delay is reduced and transistor density improves, but heat removal becomes more difficult due to high thermal resistance and power density
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat removal paths. Thermal vias are formed through multiple layers (first semiconductor layer, first interlayer dielectric, second semiconductor layer, second interlayer dielectric) to conduct heat vertically from hot spots to heat sink structures, adding a vertical dimension to heat management in 3D stacked devices
Solution Approach 2:
The patent introduces thermal vias as intermediary structures that bridge hot regions and heat sink structures. These vias act as thermal conduits, transferring heat from internal hot spots through intermediate dielectric layers to external heat dissipation structures, enabling efficient heat removal without compromising the 3D stacking architecture
2Reliability
If metal layers are precisely aligned and bonded in 3D stacked structures, then device performance and power distribution integrity improve, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent forms alignment marks and bonding pads on the first semiconductor layer before stacking the second semiconductor layer. These preliminary structures enable precise alignment during the bonding process, ensuring that through-vias in the second layer correctly connect to metal interconnects in the first layer, thereby maintaining power distribution integrity while managing alignment precision requirements
Solution Approach 2:
The patent replaces mechanical alignment methods with field-based alignment using alignment marks that are optically or electronically detected. This substitution enables more precise alignment through non-contact measurement and positioning systems, reducing the mechanical tolerance requirements for bonding processes in 3D stacked device fabrication
Data Source
AI summary
A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.