3D Semiconductor Stack With Sub-500 nm TSV Alignment
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Solution Overview
Problem
Current 3D IC technologies face limitations in TSV density due to misalignment issues, high processing temperatures, and the use of non-single crystal silicon, which affect performance and reliability, making it difficult to achieve high-density, low-power consumption integrated circuits.
Innovation Solution
The use of single crystal silicon layers with aligned transistors and through-silicon vias (TSVs) of less than 500 nm diameter, allowing for high-density interconnects and reduced alignment errors, along with low-temperature processing to maintain transistor performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional TSV fabrication methods are used, then through-silicon vias can be formed, but alignment errors and limited density occur due to misalignment issues and large TSV diameters
Solution Approach 1:
The patent changes the fundamental parameter of TSV diameter from micrometer scale (1-10 microns in conventional methods) to nanometer scale (less than 500 nm), enabling millions of interconnections per chip compared to thousands in conventional approaches. This parameter change directly resolves the contradiction by allowing both high precision alignment and high density interconnections.
2Ease of manufacture
If high processing temperatures are used, then fabrication can proceed, but transistor performance and reliability deteriorate
Solution Approach 1:
The patent changes the processing temperature parameter from high temperatures (conventional fabrication temperatures) to low temperatures (below 200°C), enabling the formation of nanometer-scale TSVs and high-k metal gate transistors without degrading transistor performance or reliability, thus resolving the contradiction between manufacturability and reliability.
3Ease of manufacture
If non-single crystal silicon is used, then fabrication is easier, but performance and reliability are reduced
Solution Approach 1:
The patent changes the material parameter from non-single crystal silicon to single crystal silicon, enabling the formation of high-quality nanometer-scale TSVs and high-k metal gate transistors with excellent electrical properties and reliability, resolving the contradiction between fabrication ease and device reliability.
4Ease of manufacture
If large TSV diameters are used, then fabrication is simpler, but interconnection density and performance are limited
Solution Approach 1:
The patent changes the TSV diameter parameter from large (1-10 microns) to small (less than 500 nm), enabling millions of interconnections per chip while maintaining fabrication feasibility through low-temperature processing and single crystal silicon materials, thus resolving the contradiction between fabrication simplicity and interconnection density.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.