3D Stacked Integrated Circuits with Fluid-Assisted Wafer Alignment
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Solution Overview
Problem
Two-dimensional scaling in semiconductor fabrication has reached limitations at the 7 nm node due to challenges in metrology precision and feature size, making it difficult to continue beyond this technology node.
Innovation Solution
The method involves assembling source wafers onto product wafers using precision overlay techniques, where fluid is deployed between die regions to enable precise alignment and stacking, and Through Silicon Vias or Inter Layer Vias are used for connectivity, allowing for three-dimensional stacking of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional scaling is used to continue semiconductor fabrication, then transistor density increases, but metrology precision requirements exceed atomic scale limitations
Solution Approach 1:
The patent transitions from two-dimensional scaling to three-dimensional stacking by vertically stacking multiple semiconductor wafers. This dimensional change allows continued increase in transistor density without further reducing lateral feature sizes to impossible precision levels. The overlay precision requirement of sub-50 nm enables this vertical integration approach.
Solution Approach 2:
The patent divides the semiconductor fabrication process into separate wafer stages that are fabricated independently and then stacked. Each wafer can be optimized separately, and the stacking process with precision overlay aligns corresponding features across wafers. This segmentation allows continuation of scaling by adding vertical layers rather than continuously shrinking lateral dimensions.
2Length of moving object
If feature dimensions are reduced to atomic scales for continued 2D scaling, then transistor density increases, but manufacturing precision becomes impossible to achieve
Solution Approach 1:
Instead of continuing to reduce feature dimensions in two dimensions, the patent moves to three-dimensional stacking where moderate-sized features are stacked vertically. This avoids the need to fabricate features at impossible precision levels while still achieving increased device density through the third dimension.
Solution Approach 2:
The patent performs preliminary fabrication of complete wafers at achievable precision levels, then uses precision overlay during stacking to achieve the final high-density configuration. This preliminary action allows each wafer to be fabricated at realistic precision levels before combination, avoiding the need for impossible single-step precision.
3Quantity of substance
If multi-patterning technologies are used to increase transistor density, then device capacity increases, but overlay precision requirements approach atomic scale
Solution Approach 1:
The patent achieves increased device capacity through vertical stacking rather than through multi-patterning that requires extreme overlay precision. By moving to the third dimension, the system can increase capacity with more moderate overlay precision requirements of sub-50 nm.
Solution Approach 2:
The patent introduces a fluid intermediary between wafers during the stacking process to enable precision overlay. This fluid mediator facilitates the alignment and bonding process, making it possible to achieve the required sub-50 nm precision without the extreme precision demands of traditional multi-patterning approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the continuation of semiconductor scaling beyond the 7 nm node by achieving sub-50 nm overlay precision and facilitating the construction of three-dimensional integrated circuits with improved performance and reduced footprint.
Implementation Method 1
fluid is deployed between the die regions on the source wafer and the product wafer
Implementation Method 2
precision overlay is enabled by a fluid deployed between the die regions
Data Source
AI summary
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).