3D Stacked Integrated Circuits With Sub-50 Nm Wafer Overlay
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Solution Overview
Problem
Two-dimensional scaling in semiconductor fabrication has reached its limits due to atomic scale dimensions and metrology precision challenges, making it difficult to continue beyond the 7 nm node.
Innovation Solution
A method for assembling wafers using precision overlay and alignment metrology, involving fluid deployment and pick-and-place strategies to stack source wafers in three-dimensional configurations, connected by Through Silicon Vias or Inter Layer Vias, utilizing standard 2D semiconductor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D scaling is continued to increase transistor density, then transistor count increases, but manufacturing precision requirements become impossible to meet at atomic scales
Solution Approach 1:
The patent transitions from two-dimensional scaling to three-dimensional wafer stacking to continue increasing transistor density. By stacking multiple wafers vertically with sub-50 nm precision overlay, the invention achieves higher effective transistor density without further reducing lateral feature dimensions to atomic scales, thereby avoiding the metrology precision limitations of continued 2D scaling.
2Productivity
If feature dimensions are reduced to atomic scales to maintain Moore's law, then transistor density increases, but the thickness of capping layers approaches atomic dimensions making fabrication infeasible
Solution Approach 1:
Instead of continuing to reduce lateral feature dimensions to atomic scales, the patent stacks wafers in the third dimension with precise sub-50 nm overlay control. This approach maintains feasible lateral feature dimensions while achieving increased transistor density through vertical integration, avoiding the capping layer thickness control problems that would arise from continued 2D scaling.
3Productivity
If multi-patterning technologies are used to increase transistor density, then transistor count increases, but overlay precision requirements approach 0.2 nm which is less than one silicon atom width
Solution Approach 1:
The patent performs the overlay operation in the third dimension by stacking wafers vertically, achieving sub-50 nm precision overlay between stacked wafers. This 3D stacking approach avoids the impossible 0.2 nm overlay precision requirements of 2D multi-patterning while still achieving high transistor density through vertical integration.
Solution Approach 2:
The patent introduces a fluid intermediary between the wafers during the stacking process to enable precise positioning and alignment. The fluid allows for controlled manipulation and sub-50 nm overlay precision achievement without requiring direct mechanical contact that would be impossible to control at the required precision level.
4Ease of operation
If conventional pick-and-place methods are used to assemble dies, then device assembly is achieved, but sub-50 nm overlay precision cannot be maintained
Solution Approach 1:
The patent introduces a fluid intermediary during the pick-and-place assembly process that enables both ease of operation and sub-50 nm overlay precision. The fluid allows for controlled manipulation of wafers while maintaining the precise positioning needed for high-precision overlay, overcoming the limitation of conventional dry pick-and-place methods.
Solution Approach 2:
The patent employs fluid-based (pneumatic or hydraulic) mechanisms to achieve precise wafer positioning and overlay during assembly. The fluid pressure and flow control enable sub-50 nm precision positioning while maintaining ease of operation, combining the benefits of automated assembly with high-precision alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables sub-50 nm overlay between die layers, facilitating the construction of three-dimensional integrated circuits with improved performance and reduced footprint.
Implementation Method 1
the precision overlay comprises a difference between a vector position of points on one or more of the die regions and a vector position of corresponding points on the product wafer
Implementation Method 2
utilizing a fluid to allow lubricated relative motion between the first wafer and the second wafer
Data Source
AI summary
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).