3D Stacked CNT-TFT Circuit with Dielectric Mediator
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Solution Overview
Problem
Current methods for integrating n-type and p-type carbon nanotube thin film transistors (TFTs) face challenges in achieving compact, stable, and efficient integration, with existing solutions being unstable and prone to contamination, and requiring high temperatures that compromise device size and performance.
Innovation Solution
A 3D complementary metal oxide semiconductor (CMOS) carbon nanotube thin film transistor circuit is developed, where n-type and p-type TFTs are stacked with a shared gate electrode, using a functional dielectric layer to convert p-type to n-type and isolate from oxygen and water, and a through hole structure to connect electrodes, allowing for compact and stable integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alkali metal or organic polymer doping is used to create n-type TFTs, then high-performance n-type TFTs are achieved, but the dopants are unstable and flowable causing contamination of nearby p-type TFTs
Solution Approach 1:
The patent introduces an inorganic dielectric layer as an intermediary between the dopant and the carbon nanotube channel. This dielectric layer contains the dopant atoms (such as phosphorus or arsenic) and releases them gradually to dope the channel, preventing direct contact and potential contamination while maintaining stable doping. The dielectric acts as a mediator that controls dopant delivery without the instability issues of organic polymers or alkali metals.
2Area of stationary object
If compact integration of n-type and p-type TFTs is achieved using standard photolithography, then device size is reduced, but existing methods require large shadow masks beyond photoresist endurance
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical integration by stacking n-type and p-type TFTs in different layers. This allows compact integration without requiring large shadow masks, as the dopant delivery and device formation occur in the vertical dimension through the dielectric layer rather than laterally through large-area shadow masking.
3Reliability
If covering materials are grown at high temperature to isolate oxygen and water, then p-type TFT stability is improved, but the temperature exceeds photoresist endurance requiring large shadow masks
Solution Approach 1:
The patent segments the processing into distinct temperature stages: first forming the carbon nanotube network and dielectric layer at low temperatures compatible with photoresist, then performing high-temperature dopant delivery and isolation in subsequent steps. This allows the photoresist to complete its function at low temperature before high-temperature processing removes the need for shadow masks.
4Stability of the object's composition
If sparse integration is used to prevent contamination from flowable dopants, then dopant stability is maintained, but device density and integration level are reduced
Solution Approach 1:
The inorganic dielectric layer serves as a containment intermediary that allows high-density integration without dopant contamination. By trapping dopant atoms within the dielectric matrix and controlling their release, the system achieves both high integration density and dopant stability, eliminating the need for sparse integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-performance, compact, and stable integration of n-type and p-type TFTs, achieving low static power consumption, large noise margin, and flexibility in device size and application, with excellent electrical and mechanical properties even under bending conditions.
Implementation Method 1
a functional dielectric layer to convert p-type to n-type and isolate from oxygen and water
Implementation Method 2
SWCNT-TFTs show p-type characteristics in ambient conditions because of the adsorption of oxygen and water vapor
Data Source
AI summary
A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.