3D Stacked Computing Architecture Dynamic Interconnects
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Solution Overview
Problem
High performance computing (HPC) systems face limitations in energy efficiency and throughput per unit area due to architectural constraints, particularly in multi-tile processor integrated circuits, where advances in component performance are bounded by fundamental socket and board-level limitations.
Innovation Solution
The implementation of a three-dimensional dataflow computing architecture with multiple physical layers, including a physical network layer, a computing layer, and a memory layer, which allows for dynamic reconfiguration of interconnect topologies and reduces data transport distances, enabling more efficient data movement and computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-tile processor ICs are used to improve computing performance, then processing capability increases, but energy efficiency and throughput per unit area are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar integration to three-dimensional stacked architecture, where multiple processor tiles are vertically stacked and interconnected through through-silicon vias (TSVs). This dimensional change enables shorter data transport paths, reduced energy consumption, and higher throughput per unit area by exploiting the third dimension for both computation and interconnect.
Solution Approach 2:
The patent implements a hierarchical nested structure where processor tiles are stacked within a three-dimensional integrated circuit package, with each tile containing nested functional units (cores, caches, interconnect). The TSVs penetrate through multiple layers, creating a nested interconnect structure that enables efficient vertical communication between stacked tiles.
2Productivity
If more processor tiles are integrated on a die to increase performance, then computing capability improves, but throughput per unit area and energy efficiency are bounded
Solution Approach 1:
The patent uses three-dimensional stacking to increase the number of processor tiles within the same footprint area. By vertically stacking multiple tiles and connecting them via TSVs, the system achieves higher throughput per unit area without being constrained by planar scaling limitations.
3Productivity
If component performance is advanced while maintaining stable division of labor, then incremental performance improvement is achieved, but further advancement is bounded
Solution Approach 1:
The patent implements dynamically reconfigurable interconnect networks that can adaptively route data between different functional units based on workload requirements. This dynamic architecture allows the system to optimize the division of labor between components at runtime, enabling performance improvements beyond fixed architectural constraints.
Solution Approach 2:
The patent designs universal processor tiles with heterogeneous functional units (GPUs, DPUs, NPU, etc.) that can perform multiple types of computations. The reconfigurable interconnect fabric enables these universal tiles to dynamically allocate resources for different workloads, increasing architectural flexibility and performance scalability.
Data Source
AI summary
Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.