3D Stacked 1T1C DRAM Structure for Higher Memory Density
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Solution Overview
Problem
The challenge of scaling DRAM devices to increase memory density is hindered by the need for large capacitor configurations, which are difficult to achieve in single-layer configurations.
Innovation Solution
The development of 3D stacked DRAM structures, where each layer comprises a bit line and a plurality of memory cells with transistors and capacitors oriented in a single plane, allowing for vertical stacking and increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-layer DRAM configuration is used, then device structure is simple, but memory density cannot be increased
Solution Approach 1:
The patent transitions from a single-layer planar configuration to a three-dimensional stacked configuration by adding the vertical dimension. Multiple DRAM layers are stacked vertically with each layer containing memory cells, allowing memory density to increase without proportionally increasing planar area, thus resolving the contradiction between structural simplicity and memory density
2Quantity of substance
If large capacitor configuration is used, then capacitor capacity is sufficient, but fabrication difficulty increases
Solution Approach 1:
The patent divides the large capacitor requirement into multiple smaller capacitors distributed across different layers. Each layer contains capacitors that collectively provide the required total capacity, making fabrication easier as each individual capacitor is smaller and more manageable while achieving the same total capacitance
3Quantity of substance
If trench-like capacitor or COB capacitor is formed, then capacitor capacity is increased, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent merges the capacitor formation process with the standard metal layer fabrication process. Capacitors are formed using the same metallization layers and processing steps as the interconnect structure, eliminating the need for separate trench formation or COB capacitor structures, thus reducing device complexity while maintaining adequate capacitor capacity
Data Source
AI summary
Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.