3D Stacked DRAM Cell With Inversion Channel For Density Scaling
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Solution Overview
Problem
The shrinking feature size of semiconductor devices for dynamic random access memory (DRAM) complicates the scaling down of capacitor areas, making it difficult to improve integration and scalability, particularly in the preparation process.
Innovation Solution
A semiconductor device structure with a substrate featuring memory cell columns, transistors, and capacitors, where the semiconductor layer includes a source region, channel region, and drain region, with the channel region being an inversion channel region, and word lines of varying lengths forming a staircase shape, along with interlayer isolation and memory cell isolation posts, to enhance memory density and reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the feature size of semiconductor devices is shrunk to improve integration and scalability, then memory density increases, but the preparation process becomes more complex and capacitor area scaling becomes difficult
Solution Approach 1:
The patent transitions from planar memory cell layout to a three-dimensional stacked architecture where memory cells are arranged vertically in multiple layers. Multiple bit lines extend in the first direction, word lines in the third direction, and memory cell columns are stacked along the first direction, utilizing the third dimension to increase memory density without proportionally increasing substrate area or process complexity
Solution Approach 2:
The memory device is divided into multiple independent memory cell columns, each containing stacked memory cells. Each memory cell is segmented into distinct functional components (transistor with source/channel/drain regions, gate, and capacitor) that can be independently formed and controlled, simplifying the overall preparation process while maintaining high density
2Length of stationary object
If the feature size is reduced for miniaturization, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor is positioned within or adjacent to the transistor structure, with the transistor gate surrounding the channel region and the capacitor surrounding an end of the drain region. This nested arrangement allows compact integration of capacitor structures within the transistor footprint, reducing overall device size while maintaining manufacturing precision through standardized formation processes
Solution Approach 2:
The patent employs inversion channel regions where the semiconductor material polarity in the channel differs from source and drain regions. This parameter change enables precise control of channel characteristics and threshold voltages, allowing accurate device performance control even at reduced dimensions where traditional scaling approaches become difficult
3Quantity of substance
If memory cells are stacked vertically to increase density, then memory density improves, but device structure complexity increases
Solution Approach 1:
The gate structures serve dual functions: as control electrodes for individual transistors within memory cells, and collectively as word lines that can be connected together to form common control signals across multiple memory cell columns. This multi-functionality reduces the number of separate components needed, simplifying the overall device structure while maintaining high vertical stacking density
Solution Approach 2:
Gates of transistors from multiple memory cell columns are connected together to form shared word lines. Bit lines from adjacent memory cell columns are also merged to share common conductors. This merging approach reduces the total number of independent interconnects needed, decreasing device structure complexity while preserving the benefits of vertical stacking for memory density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves memory density, reduces manufacturing costs per unit Gb, and provides a high on-state current and switching ratio, addressing the challenges of miniaturization in DRAM technology.
Implementation Method 1
the channel region of the semiconductor layer is an inversion channel region
Data Source
AI summary
The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.