3D Stacked Dual-Gate Thin-Film Transistors for Logic Integration
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Solution Overview
Problem
Current technologies face limitations in increasing the degree of integration of transistors beyond Moore's Law, particularly in three-dimensional space, and struggle to apply three-dimensional stacking effectively to CMOS silicon transistors due to physical and cost constraints, while thin-film transistors offer potential but are challenging to integrate into circuits.
Innovation Solution
A logic circuit using three-dimensionally stacked dual-gate thin-film transistors, where multiple transistors are electrically connected to function as a single logic gate, allowing for increased integration and simplified wiring, utilizing a stacked configuration with shared electrodes and independent control of gate electrodes to implement NAND and NOR gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacking of transistors is implemented, then the degree of integration is improved, but the device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertical stacking, where multiple transistor layers are stacked on top of each other. This dimensional change allows significantly higher integration density without proportionally increasing wiring complexity, as connections are made through vertical vias rather than extensive lateral routing.
Solution Approach 2:
The patent implements nested transistor structures where source and drain electrodes of lower-layer transistors serve as gate electrodes for upper-layer transistors. This nesting approach reduces the total number of separate electrodes required, thereby decreasing device complexity while maintaining high integration density.
2Ease of manufacture
If thin-film transistors are used for three-dimensional stacking, then ease of manufacture is improved, but electrical mobility deteriorates
Solution Approach 1:
The patent modifies the physical and chemical parameters of the thin-film semiconductor material through controlled deposition processes, annealing treatments, and compositional adjustments. These parameter changes enhance carrier mobility in the thin-film transistor channels while preserving the manufacturing advantages of thin-film technology, including low-temperature processing and large-area fabrication capability.
Data Source
AI summary
Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.