3D Stacked GAA Transistors for Density and N/P Balance
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Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, two-dimensional transistor scaling faces challenges due to limitations in contacted gate pitch and wire pitch scaling, leading to reduced transistor density and performance imbalances between NMOS and PMOS transistors, which are exacerbated by the transition from finFET to Lateral Gate All Around (LGAA) nanosheet architectures.
Innovation Solution
The development of a 3D semiconductor device with vertically stacked gate-all-around (GAA) transistors using alternating material layers to form both NMOS and PMOS transistors, where each stack includes channel regions made of different materials (e.g., silicon, silicon carbide, germanium, or silicon-germanium) with vertically offset structures, enabling better performance and increased density by leveraging intrinsic compressive biaxial strain in SiGe channels for enhanced hole mobility and Vt tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued to increase transistor density, then transistor density improves, but contacted gate pitch and wire pitch scaling face limitations that prevent further density improvement
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor layers are stacked in the vertical direction (thickness direction of substrate), enabling increased transistor density without further reduction in contacted gate pitch. The vertical stacking architecture allows transistors to be arranged in multiple layers, effectively utilizing the third dimension to overcome the limitations of 2D scaling.
2Reliability
If finFET architecture is used, then transistor performance is maintained, but transition to LGAA nanosheet architecture causes performance imbalances between NMOS and PMOS transistors
Solution Approach 1:
The patent applies different channel materials to different transistor types within the stacked architecture. Silicon channels are used for NMOS transistors while silicon-germanium alloys are used for PMOS transistors. This local material differentiation optimizes the electrical properties for each transistor type, achieving better N/P current balance in the LGAA architecture by tailoring the channel material composition to the specific requirements of each device type.
Solution Approach 2:
The patent employs composite material structures with alternating layers of silicon and silicon-germanium. The silicon-germanium alloy layers provide different bandgap and mobility characteristics compared to pure silicon, enabling independent optimization of NMOS and PMOS performance. This composite material approach allows the LGAA architecture to achieve both high performance and balanced N/P characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances circuit performance by improving N/P current balance, increasing transistor density, and providing more Vt options, thus overcoming scaling limitations and achieving better performance for both NMOS and PMOS devices in 3D logic circuits.
Implementation Method 1
The initial stack of layers can be patterned so that the initial stack of layers is divided into a first stack and a second stack, where the first stack and the second stack are adjacent to each other. First gate-all-around (GAA) transistors can be formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors.
Implementation Method 2
enabling better performance and increased density by leveraging intrinsic compressive biaxial strain in SiGe channels for enhanced hole mobility and Vt tuning
Data Source
AI summary
A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.