3D Stacked GaN Amplifier Reducing Heat Flux
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Solution Overview
Problem
Conventional RF power amplifiers face thermal limitations due to the proximity of transistors, leading to heat concentration and reduced performance, particularly in linear binomial feed and combiner amplifier networks where transistors are closely packed, restricting cooling and increasing heat flux.
Innovation Solution
A three-dimensional architecture using two substrates with high electron mobility transistors, where a first substrate with GaN transistors is coupled via microstrip interconnects and a second substrate with silicon transistors via stripline interconnects, allowing for increased spacing between transistors and minimizing heat flux by distributing RF transmission lines in three dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are placed close to one another in linear binomial feed and combiner amplifier networks, then the amplifier network can be implemented following foundry design rules, but the thermal load is concentrated and heat flux increases in a given area
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar arrangement of transistors to a three-dimensional stacked architecture where transistor circuits are distributed across multiple substrates vertically arranged. This dimensional change allows transistors to be spaced further apart while maintaining electrical connectivity through vertical interconnects, thereby reducing heat flux concentration in any single area while complying with design rules.
Solution Approach 2:
The amplifier network is segmented into multiple independent transistor circuits distributed across different substrates. Each substrate contains a portion of the overall transistor circuitry, allowing thermal loads to be distributed across multiple locations rather than concentrated in a single planar area, thus reducing heat flux while maintaining functional integrity.
2Area of stationary object
If transistors are placed close to one another to achieve compact amplifier networks, then the device footprint is reduced, but the cooling capability is restricted and heat flux increases
Solution Approach 1:
By stacking substrates vertically, the patent achieves a compact overall device footprint while creating additional thermal management pathways through the vertical dimension. The multi-substrate architecture allows heat to be dissipated across multiple surfaces and volumes, improving cooling capability without requiring a larger planar footprint.
Solution Approach 2:
The patent implements a nested architecture where multiple substrate layers are stacked vertically, with each substrate containing transistor circuits that are electrically connected through vertical interconnects. This nesting approach consolidates the amplifier network into a compact three-dimensional structure while distributing thermal loads across multiple nested layers, enhancing both compactness and thermal management.
3Temperature
If a three-dimensional stacked substrate architecture is used to distribute transistor circuits, then heat flux is reduced and cooling capability improves, but the device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to stack substrates, which simplifies thermal management by distributing heat sources across multiple vertical layers with access to independent cooling pathways. While this adds vertical complexity, it actually reduces overall system complexity compared to achieving the same thermal performance through elaborate planar heat sinking arrangements.
Data Source
AI summary
The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system may include a plurality of high electron mobility transistors disposed on a first substrate. A first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate. The system also includes a plurality of second level interconnects disposed on a second substrate. A second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects. The first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides an amplified output signal via at least one of the first level interconnects or the second level interconnects.