3D Stacked Gate Driver IC Eliminates Termination Regions
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Solution Overview
Problem
Conventional high voltage gate driver integrated circuits are large in size due to the need for wide junction termination regions to ensure breakdown voltages of 600V or more, and they require additional processing steps and buried layers, increasing manufacturing costs and complexity.
Innovation Solution
A three-dimensional gate driver integrated circuit is designed with a high-side integrated circuit stacked on a low-side integrated circuit, interconnected using through-silicon vias, eliminating the need for termination regions and buried layers, and forming separate high voltage and low voltage circuit regions to improve integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide junction termination region is used to ensure breakdown voltage of 600V or more, then reliability is improved, but the area of the integrated circuit increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture, where the high-side integrated circuit is positioned vertically above the low-side integrated circuit. This dimensional change allows the junction termination region to be distributed in the vertical direction rather than consuming horizontal area, thereby maintaining the required breakdown voltage while reducing the overall chip footprint.
Solution Approach 2:
The integrated circuit is segmented into separate high-side and low-side circuits that are vertically stacked and electrically isolated. The junction termination region is specifically allocated to the high-side circuit region, separating its function from the low-side circuit. This segmentation allows the termination region to be optimized for high voltage without constraining the low voltage circuit area.
2Reliability
If N-type buried layer structure is formed to provide low resistance path and prevent latch-up, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the N-type buried layer structure from the conventional high voltage gate driver circuit. By eliminating this component, the patent reduces the number of fabrication processing steps and simplifies the device structure, while maintaining reliability through the three-dimensional stacked architecture and dedicated high voltage circuit region.
3Reliability
If N-type buried layer structure is formed to provide low resistance path, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent eliminates the N-type buried layer structure, thereby removing the associated fabrication processing steps. This extraction reduces manufacturing complexity and cost while maintaining reliable parasitic substrate conduction control through the three-dimensional stacked architecture and proper isolation design between high and low voltage regions.
Data Source
AI summary
A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.