3D Stacked Semiconductor Gate Structure for Higher MOSFET Integration
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Solution Overview
Problem
As semiconductor devices are scaled down to achieve smaller pattern sizes and higher performance, the operating characteristics of MOSFETs deteriorate, leading to challenges in developing methods for fabricating semiconductor devices with superior performance and increased integration.
Innovation Solution
A three-dimensional semiconductor device is designed with a stacked structure, including a first active region with lower channel and source/drain patterns, and a second active region with upper channel and source/drain patterns. The device features gate electrodes that connect lower and upper gate electrodes through an isolation pattern, allowing for a cross-couple structure that increases integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to achieve smaller pattern sizes, then the area of the semiconductor device is reduced, but the operating characteristics of the MOSFETs deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by vertically stacking multiple active regions (first active region with lower channel, second active region with upper channel) above each other. This vertical stacking allows multiple transistors to be integrated within a smaller footprint area while maintaining adequate channel dimensions for proper MOSFET operation, thus resolving the contradiction between reducing device area and maintaining operating characteristics.
2Productivity
If MOSFETs are scaled down to achieve higher integration, then the number of transistors per area increases, but the operating characteristics deteriorate
Solution Approach 1:
The invention utilizes vertical stacking to achieve higher integration density by stacking transistors in the third dimension (vertical direction). The first active region and second active region are positioned at different vertical levels, allowing multiple transistor channels to coexist within a compact area without forcing lateral scaling that would degrade channel performance.
Solution Approach 2:
The transistor structure is segmented into distinct vertical sections: lower channel in the first active region, upper channel in the second active region, with separate gate electrodes (first gate electrode, second gate electrode) controlling each channel independently. This segmentation allows each channel to be optimized for proper operation while achieving high integration through vertical stacking.
3Productivity
If three-dimensional stacked structure is implemented to increase integration, then the number of transistors per package doubles, but the device complexity increases
Solution Approach 1:
The first gate electrode and second gate electrode are connected through a conductive structure, merging them into an integrated gate system. This merging approach simplifies the overall device structure by reducing the number of independent gate control lines needed, thereby managing device complexity while maintaining the high integration benefit of the stacked configuration.
Data Source
AI summary
Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.