3D Stacked IC Assembly With Sub-50 Nm Wafer Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional scaling in semiconductor fabrication has reached its limits due to atomic scale dimensions and metrology precision challenges, making it difficult to continue beyond the 7 nm node.
Innovation Solution
A method for assembling wafers using precision overlay and alignment metrology, involving fluid deployment and superstrate attachment, to stack source wafers with device layers fabricated using standard 2D semiconductor processes, allowing for face-to-face, face-to-back, back-to-face, or back-to-back configurations connected by Through Silicon Vias or Inter Layer Vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D scaling is continued to increase transistor density, then transistor count increases, but manufacturing precision requirements become impossible to meet at atomic scales
Solution Approach 1:
The patent transitions from two-dimensional scaling to three-dimensional stacking of integrated circuit layers. By stacking multiple 2D dies vertically with precise alignment (sub-50 nm overlay precision), the system achieves continued transistor density improvement without requiring further reduction of lateral feature dimensions, thus avoiding the atomic-scale precision limitations of 2D scaling.
2Quantity of substance
If feature dimensions are reduced to atomic scales to maintain Moore's law, then transistor density increases, but metrology precision requirements become unachievable
Solution Approach 1:
Instead of continuing to reduce lateral feature dimensions to atomic scales (which would require unachievable metrology precision), the patent stacks multiple 2D dies in the vertical dimension. This approach maintains achievable lateral metrology precision while achieving continued density improvement through vertical integration.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate 2D dies that are fabricated independently using standard 2D processes, then stacked vertically. Each die can be manufactured with conventional precision requirements, and the overall system achieves high density through the segmented, multi-layer architecture.
3Device complexity
If conventional top-down fabrication is used to maintain manufacturing simplicity, then process complexity remains low, but scaling beyond 7 nm node becomes infeasible
Solution Approach 1:
The patent segments the fabrication process into two parts: (1) conventional top-down fabrication of individual 2D dies using standard processes, and (2) subsequent stacking and bonding of these dies in the vertical dimension. This segmentation allows each die to be manufactured with simple, conventional processes while the overall system achieves high density through the segmented stacking approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the construction of three-dimensional stacked integrated circuits with sub-50 nm overlay precision, overcoming scaling limitations and facilitating efficient integration of transistors and interconnects.
Implementation Method 1
precision overlay is enabled by a fluid deployed between the die regions on the source wafer and the product wafer
Implementation Method 2
assembling utilizes a combination of a superstrate z-force, a controlled outward airflow from a bonding interface
Data Source
AI summary
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).