3D Stacked IC Reconfiguration for Column-Level Failure Bypass
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Solution Overview
Problem
Three-dimensional stacked integrated circuits (3D ICs) face challenges in failure management due to various causes such as excess temperature, voltage, radiation, and mechanical stress, which can lead to premature device failure, and existing technologies lack effective mechanisms to manage these failures efficiently.
Innovation Solution
The implementation of configurable routes within 3D ICs allows for bypassing failed functional blocks or layers, enabling rerouting of resources and preventing catastrophic failure by utilizing TSVs and error detecting logic circuits to monitor and reconfigure connections dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D ICs are used to shorten electrical paths and reduce footprint, then device performance and integration density are improved, but vulnerability to failures from temperature, voltage, radiation, and mechanical stress increases
Solution Approach 1:
The 3D IC is divided into multiple functional blocks that can be independently monitored and managed. Each functional block can be individually bypassed if it fails, allowing the rest of the system to continue operating. This segmentation enables localized failure management without catastrophic system-wide failure.
Solution Approach 2:
Error detecting logic circuits continuously monitor the operational status of functional blocks and provide feedback signals. When a failure is detected, the feedback triggers automatic rerouting through alternative paths, enabling real-time failure management and maintaining system reliability despite the high-density 3D architecture.
2Reliability
If functional blocks are bypassed upon failure, then system reliability is improved, but device complexity increases due to configurable routes and error detecting logic
Solution Approach 1:
Alternative routes and error detecting logic are pre-configured into the 3D IC architecture before operation. When a failure occurs, the system can immediately activate these pre-prepared bypass paths without requiring complex real-time decision-making or reconfiguration, thus managing failure reliably while limiting the increase in operational complexity.
3Measurement precision
If error detecting logic circuits are implemented, then failure detection capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The error detecting logic circuits are integrated directly into the functional blocks of the 3D IC, merging the detection function with the existing architecture. This integration approach allows failure detection capability to be added without requiring separate external monitoring systems, thereby improving manufacturing efficiency and reducing overall system complexity despite the added detection functionality.
Data Source
AI summary
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.