3D Stacked Image Sensors with Oxide-to-Oxide Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current image sensors face challenges such as limited light sensitivity due to the integration of photodetectors and sensing circuitry on the same chip, alignment issues in stacking technologies like TSV, and the sequential shifting of image information in CCD sensors, which affects speed and cell density, as well as the tradeoff between dynamic range and picture quality in HDR imaging.
Innovation Solution
The use of layer transfer technology to monolithically stack photodetectors and read-out circuits, allowing for parallel data collection and the integration of image sensors with distinct light-sensitive areas and insulating layers, along with algorithms for reconstructing objects and gesture recognition systems using dual image sensor arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If photodetectors and sensing circuitry are integrated on the same chip, then device complexity is reduced, but light sensitivity deteriorates due to area consumption by sensing circuits
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by separating photodetectors and sensing circuitry into different layers. The first sub-array with photodetectors is positioned at a first depth, while the second sub-array with sensing circuitry is positioned at a second depth, enabling spatial separation that improves light sensitivity while maintaining integration.
Solution Approach 2:
The image sensor array is segmented into multiple sub-arrays positioned at different depths within the semiconductor structure. The first sub-array contains photodetectors for light detection, while the second sub-array contains sensing circuitry for signal processing, allowing functional separation that resolves the contradiction between integration and sensitivity.
2Measurement precision
If TSV stacking technology is used to separate photodetectors and sensing circuitry, then light sensitivity improves, but manufacturing precision deteriorates due to alignment issues
Solution Approach 1:
The patent introduces a semiconductor layer as an intermediary medium between the first and second sub-arrays. This intermediate layer facilitates the bonding and alignment processes, providing a stable platform for attaching the photodetector array to the sensing circuitry array, thereby improving manufacturing precision during the stacking process.
Solution Approach 2:
The patent performs preliminary processing of the semiconductor layer before final assembly, including depositing the layer on a release structure and preparing bonding surfaces. These preliminary actions establish precise geometric relationships and alignment features before the actual stacking, reducing alignment issues during manufacturing.
3Device complexity
If CCD sequential shifting is used for image information transfer, then device complexity is reduced, but speed deteriorates due to sequential processing
Solution Approach 1:
The patent enables parallel signal processing by positioning multiple sensing circuitry elements at different depths along the vertical dimension. This 3D arrangement allows simultaneous processing of multiple pixel signals through different sub-arrays, transitioning from sequential CCD shifting to parallel processing, thereby improving image processing speed while maintaining relatively simple device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances light sensitivity, improves pixel alignment, and achieves higher dynamic range and faster image processing, enabling more efficient and effective image capture and reconstruction in various applications.
Implementation Method 1
wherein the second level is bonded to the first level, and wherein the bonded comprises an oxide to oxide bond
Data Source
AI summary
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors and alignment marks; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the third level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.