3D-Stacked Imaging Semiconductor Structure for Mixed-Node Circuits
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Solution Overview
Problem
Existing imaging devices face challenges in integrating circuit chips with different technology nodes due to structural limitations, particularly in arranging advanced logic circuits with low power supply voltage alongside analog circuits requiring high power, which hinders high-speed signal output and functional integration.
Innovation Solution
A semiconductor device with a three-dimensional structure is developed, featuring stacked chip-on-wafer layers that accommodate circuit chips with different technology nodes, including an analog circuit with older nodes and advanced logic circuits, enabling efficient integration and high-speed signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If circuit chips with different technology nodes are integrated in a planar structure, then functional integration is achieved, but signal transmission speed decreases and parasitic capacitance increases
Solution Approach 1:
The patent transitions from a planar integration structure to a three-dimensional stacked structure. Multiple circuit chips with different technology nodes are vertically stacked and bonded together, enabling functional integration while reducing signal transmission distance. The stacked configuration allows analog circuits, logic circuits, and memory circuits to be positioned in different vertical layers, significantly reducing parasitic capacitance and improving signal speed compared to planar arrangements.
Solution Approach 2:
The patent implements a nested structure where multiple circuit chips are stacked and bonded together in a layered configuration. Each chip layer contains specific circuit functions (analog, logic, memory), and they are nested vertically with bonding interfaces connecting corresponding pads between layers. This nested stacking enables high-density integration while maintaining short signal paths between functional blocks.
2Adaptability or versatility
If analog circuits and logic circuits are placed close together, then functional integration improves, but power supply voltage compatibility becomes problematic
Solution Approach 1:
The patent segments the circuit system into separate functional chips with different technology nodes, each optimized for its specific function and power requirements. Analog circuits requiring higher voltage are placed on one chip layer, while advanced logic circuits operating at lower voltages are placed on other layers. The segmentation allows independent power supply management for each layer through separate power supply lines extending from the back surface, resolving voltage compatibility issues while maintaining functional integration.
Solution Approach 2:
The patent applies local quality by providing different power supply voltages to different regions/layers of the stacked structure. Each chip layer receives appropriate power supply voltage through dedicated power supply lines that extend from the back surface of the device. This allows analog circuits to receive higher voltage locally while logic circuits receive lower voltage, enabling functional integration without voltage compatibility conflicts.
3Speed
If multiple circuit chips are stacked vertically, then signal transmission speed increases and parasitic capacitance decreases, but device structure complexity increases
Solution Approach 1:
The patent employs a universal bonding structure that handles multiple functions through a standardized interface design. The bonding pads and connection structures are designed to accommodate different chip types and functions (analog, logic, memory) in a unified stacked architecture. Power supply lines, signal lines, and grounding structures follow standardized patterns that simplify the integration process despite the multi-functional nature of the device, reducing the impact of structural complexity.
Data Source
AI summary
A first semiconductor device according to an embodiment of the present disclosure includes: a first structure layer having a chip-on-wafer structure and being mounted with a first circuit chip and a second circuit chip that have different technology nodes; and a second structure layer having a chip-on-wafer structure and being stacked on the first structure layer.