3D Stacked Integrated Circuits for ANN Computation
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Solution Overview
Problem
Current technologies face challenges in efficiently accelerating artificial neural network (ANN) computation due to limitations in processing power and data access, leading to increased power consumption and heat generation in traditional two-dimensional integrated circuits.
Innovation Solution
The implementation of 3D stacked integrated circuits (3D SICs) with functional blocks that include non-volatile memory, volatile memory, and processing logic dies, connected via through-silicon vias (TSVs), allowing for parallel data processing and reduced computational load on the CPU by distributing data-intensive functions across multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-dimensional integrated circuits are used for ANN computation, then device complexity is lower and manufacturing is easier, but processing efficiency is insufficient and power consumption increases
Solution Approach 1:
The patent transitions from traditional two-dimensional integrated circuit layout to three-dimensional stacked architecture, where multiple dies are vertically stacked and interconnected via TSVs. This dimensional change enables simultaneous execution of multiple computational operations across different layers, significantly improving processing efficiency for ANN workloads while managing complexity through modular die design.
Solution Approach 2:
The system divides the integrated circuit into multiple separate dies stacked vertically, with each die containing specific functional blocks (e.g., memory layers, processing layers). This segmentation allows independent optimization of each layer for specific tasks, improving overall productivity while making the complex system manageable through modular construction.
2Productivity
If more processing power is added to accelerate ANN computation, then computational capability improves, but heat generation increases
Solution Approach 1:
By stacking processing layers vertically in three dimensions rather than expanding horizontally, the patent increases computational capability within a compact volume. The vertical arrangement improves heat dissipation by exposing more surface area to cooling solutions and reducing heat concentration in any single location, thereby managing temperature while maintaining high computational performance.
Solution Approach 2:
The patent implements heterogeneous computing layers with specialized functional blocks optimized for specific computational tasks (e.g., matrix multiplication, activation functions). This local optimization allows efficient processing with reduced redundant computations, lowering overall heat generation while maintaining high computational capability where needed.
3Speed
If data access speed is increased for faster ANN computation, then processing efficiency improves, but power consumption increases
Solution Approach 1:
The patent merges memory and processing functions into closely integrated layers within the same 3D stack, minimizing the physical distance data must travel between storage and computation units. This integration dramatically increases data access speed while reducing the energy required for data movement, as electrons travel shorter distances through the TSV interconnects compared to traditional separated memory-processor architectures.
Data Source
AI summary
A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.