3D Stacked Memory Cell Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of reducing parasitic capacitance and increasing capacitance in memory cells is hindered by structural limitations as memory cells are miniaturized, limiting the integration density of memory devices.
Innovation Solution
A semiconductor device with a three-dimensional structure is developed, featuring vertically stacked memory cells, including a bit line, transistor, and capacitor, with a double word line and active layer configuration, and a method for fabricating this structure through etching and replacement of sacrificial layers with double word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase net die, then memory cell density increases, but parasitic capacitance increases and structural limitations arise
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layout to three-dimensional vertical stacking architecture. Memory cells are stacked in the vertical direction (third dimension) using through-silicon vias (TSVs) and interlayer dielectric layers, enabling higher memory cell density without increasing parasitic capacitance from lateral scaling. The vertical stacking allows multiple memory cell layers to be integrated while maintaining electrical performance.
2Quantity of substance
If memory cell size is reduced, then more memory cells fit in the die, but structural limitations prevent further scaling
Solution Approach 1:
The invention moves memory cell integration from lateral scaling to vertical stacking. Multiple memory cell layers are formed by stacking active layers, gate electrodes, and interlayer dielectric layers in the vertical direction. Through-silicon vias connect bit lines and word lines across layers, enabling high-density integration without the structural constraints that limit planar scaling.
Solution Approach 2:
The patent implements nested stacking where memory cell components are arranged in concentric or layered configurations. Active layers are stacked with gate electrodes and interlayer dielectric layers in between, forming a nested three-dimensional structure. This nested architecture maximizes space utilization and achieves high memory cell density within the available vertical space.
3Quantity of substance
If three-dimensional vertical stacking is implemented, then memory cell density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent forms sacrificial layers (such as silicon nitride layers) between the active layers during the stacking process. These sacrificial layers are deposited in advance and later removed to create voids or channels for bit line and word line formation. This preliminary action simplifies the subsequent manufacturing steps by pre-defining the structural framework for vertical interconnections.
Solution Approach 2:
The invention uses interlayer dielectric layers as intermediary materials between stacked active layers. These dielectric layers provide electrical isolation and mechanical support, enabling the formation of vertical channels and vias. The sacrificial layers serve as temporary intermediaries that guide the formation of bit line and word line structures during the manufacturing process.
Data Source
AI summary
A semiconductor device includes: a substrate; a body recess in the substrate; a body dielectric layer over the body recess; an active layer extending in a direction parallel to the substrate over the substrate; a contact node over an end portion of the active layer and perpendicular to the substrate; and a conductive line coupled to the contact node and extended perpendicular to the substrate.