3D Stacked Memory Program Disturb via Channel Potential Control

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Solution Overview

Problem

The BiCS memory, which employs a three-dimensional stacked structure, faces challenges in preventing program disturb, particularly in non-selected cell units within selected blocks, due to the unique device structure and circuit operation constraints.

Innovation Solution

The proposed solution involves setting an initial plus potential as the channel potential of memory cells in non-selected cell units within selected blocks, which allows for sufficient capacitance coupling when applying program or transfer potentials to the word lines, thereby reducing program disturb.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a three-dimensional stacked structure is adopted to increase memory capacity, then memory capacity is improved, but program disturb occurs in non-selected cell units

Engineering Contradiction:
Improvememory capacityVSAvoidprogram disturb
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-charging the channel of non-selected cell units to a high potential (e.g., Vdd or Vdd-0.5V) before programming operations. This preliminary potential setup prevents threshold voltage shifts in non-selected cells during programming by ensuring their channels are already at a stable high potential, thus avoiding program disturb while maintaining the benefits of three-dimensional stacked structure for increased capacity

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If cell units are connected in series in one block to enable bit cost scalability, then bit cost scalability is improved, but circuit operation complexity increases

Engineering Contradiction:
Improvebit cost scalabilityVSAvoidcircuit operation
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by differentiating the treatment of selected and non-selected cell units within the same block. Non-selected cell units are pre-charged to a high potential to prevent program disturb, while selected cell units undergo normal programming operations. This localized differentiation allows the series-connected structure to maintain bit cost scalability while managing circuit operation complexity through selective potential application

Inventive Principle:
Principle #3Local quality

3Ease of operation

If program potential is applied to non-selected cell units in selected blocks, then programming operation is simplified, but threshold voltage variation occurs

Engineering Contradiction:
Improveprogramming operationVSAvoidthreshold voltage variation
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by establishing a high potential in the channels of non-selected cell units before programming operations. This preliminary potential setup ensures that when program potential is subsequently applied, the non-selected cells are already protected against threshold voltage shifts, thus maintaining both operational simplicity and reliability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively improves program disturb by ensuring that the channel potential of non-selected memory cells is adequately boosted, preventing variations in threshold voltage and enhancing the reliability of programming operations in BiCS memory systems.

Implementation Method 1

setting an initial plus potential as the channel potential of memory cells in non-selected cell units within selected blocks, which allows for sufficient capacitance coupling when applying program or transfer potentials to the word lines

Methodology Applied
Scientific EffectCapacitance coupling: Capacitance

Data Source

PatentUS20250087270A1Three dimensional stacked nonvolatile semiconductor memory
Publication Date: 2025.03.13 KIOXIA CORP
  • US20250087270A1 patent drawing
  • US20250087270A1 patent drawing
  • US20250087270A1 patent drawing

AI summary

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.