3D Stacked Memory Hierarchy for Bandwidth and Capacity Tradeoffs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a memory capacity gap, latency gap, and bandwidth gap between shoreline memory and fabric memory in integrated circuits, which limits the performance and efficiency of memory access due to physical constraints and power consumption issues.
Innovation Solution
A three-dimensional circuit system is introduced, featuring aquifer memory integrated circuit dies stacked vertically with the main IC die, providing additional memory capacity and bandwidth by optimizing the physical distance and power usage between memory and logic circuits, and incorporating a memory hierarchy with shoreline, aquifer, and fabric memory classes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If shoreline memory is used to increase memory capacity, then memory capacity is improved, but memory access bandwidth deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar memory integration to three-dimensional vertically stacked memory integration. Multiple memory dies are stacked in the vertical dimension, allowing memory circuits to be positioned directly above logic circuits. This spatial reconfiguration reduces access distance and increases bandwidth while maintaining high capacity through the stacked architecture.
Solution Approach 2:
The patent implements a hierarchical memory structure where fabric memory, shoreline memory, and aquifer memory are nested at different levels. The aquifer memory in the vertically stacked die provides intermediate storage between the high-speed fabric memory and the high-capacity shoreline memory, creating a nested memory hierarchy that optimizes both bandwidth and capacity.
2Quantity of substance
If shoreline memory is used to increase memory capacity, then memory capacity is improved, but memory access latency deteriorates
Solution Approach 1:
By stacking memory dies vertically above logic circuits, the patent reduces the physical access distance in the vertical dimension. This spatial reconfiguration allows faster access to memory data compared to traditional planar layouts, thereby reducing access latency while maintaining high memory capacity.
Solution Approach 2:
The patent segments memory into multiple hierarchical levels (fabric memory, aquifer memory, and shoreline memory) with different access characteristics. This segmentation allows the system to use faster fabric memory for time-critical operations while utilizing larger aquifer and shoreline memory for capacity-intensive operations, effectively managing latency across different access patterns.
3Productivity
If fabric memory is positioned near logic circuits to improve bandwidth, then memory access bandwidth is improved, but memory capacity deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple memory dies above the logic circuits. This allows fabric memory to remain positioned near logic circuits for high bandwidth access, while additional aquifer and shoreline memory capacity is provided in the vertical space above, effectively decoupling the bandwidth-capacity tradeoff.
4Quantity of substance
If vertically stacked memory dies are used to increase capacity and bandwidth, then memory capacity and bandwidth are improved, but device complexity deteriorates
Solution Approach 1:
The patent merges multiple memory dies with different characteristics (fabric memory, aquifer memory, shoreline memory) into a unified vertically stacked architecture. This consolidation provides high capacity and bandwidth through a single integrated structure, reducing the need for separate memory components and interconnections that would increase overall system complexity.
Data Source
AI summary
A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.