3D Stacked Memory Integration for High Bandwidth and Low Power
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Solution Overview
Problem
Existing electronic packaging architectures fail to provide sufficient memory capacity and bandwidth for high-performance computing (HPC) systems, leading to increased power consumption and reduced bandwidth due to lateral connections over a base substrate.
Innovation Solution
A 3D stacking architecture where a compute die is positioned over an array of memory die stacks, minimizing lateral routing and allowing direct access to memory, with power delivery paths routed through or between the die stacks, reducing power consumption and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dies are arranged over a base substrate with lateral connections, then integration density is improved, but power consumption increases and bandwidth is reduced
Solution Approach 1:
The patent transitions from a 2D lateral connection architecture to a 3D vertical stacking architecture. Memory dies are stacked vertically above the compute die, with connections made through vertical vias and interconnect layers rather than lateral routing on the base substrate. This dimensional change reduces the path length and resistance for data transfer, thereby reducing power consumption while maintaining high integration density.
2Device complexity
If dies are arranged over a base substrate with lateral connections, then integration density is improved, but bandwidth is reduced
Solution Approach 1:
By stacking memory dies vertically above the compute die, the patent creates direct vertical interconnect paths that significantly reduce the lateral distance data must travel. This 3D architecture enables shorter signal paths, lower resistance, and higher signal integrity, all of which contribute to increased bandwidth while achieving high integration density.
Solution Approach 2:
The patent segments the system into multiple stacked layers: compute die at the bottom, followed by multiple memory die stacks, with intermediate interconnect layers. This segmentation allows for dedicated vertical interconnect pathways that can operate independently, enabling parallel data transfer channels and thus increasing overall bandwidth.
3Ease of manufacture
If base substrate processing node requirements are reduced, then manufacturing yield is improved and cost is reduced, but memory capacity and bandwidth may be insufficient
Solution Approach 1:
The patent uses 3D vertical stacking to multiply memory capacity without increasing the lateral footprint of the base substrate. By stacking multiple memory dies vertically (e.g., 4-8 layers), the system achieves high memory capacity (e.g., 128GB, 256GB) while keeping the base substrate at a relaxed processing node, thereby maintaining high manufacturing yield and low cost.
Solution Approach 2:
The patent implements a nested structure where multiple memory dies are stacked within the vertical space above the compute die. Each memory die is nested within the same lateral footprint, creating a tower-like structure that maximizes memory capacity within a compact form factor while avoiding the need for advanced base substrate processing.
Data Source
AI summary
Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package comprises a package substrate and a first die electrically coupled to the package substrate. In an embodiment, an array of die stacks are electrically coupled to the first die. In an embodiment the array of die stacks are between the first die and the package substrate. In an embodiment, individual ones of the die stacks comprise a plurality of second dies arranged in a vertical stack.