3D Stacked Semiconductor Memory Integration Density
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Solution Overview
Problem
The integration density of planar semiconductor memory devices is limited by the cost and complexity of forming fine patterns, which hinders the reduction of manufacturing costs and increases the price of semiconductor memory devices.
Innovation Solution
A method involving the alternation of material layers on a substrate to form a stacked structure, with through holes and data storage layers on the sidewalls, allowing for the formation of semiconductor patterns and conductive layers that enhance integration density without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine patterns are formed in planar semiconductor memory devices to increase integration density, then integration density is improved, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory device architecture to three-dimensional (3D) stacked architecture. Multiple memory layers are stacked vertically with through-holes penetrating through the layers, allowing data storage in multiple dimensions. This vertical stacking enables higher integration density without requiring finer lateral patterning, thus avoiding the increased manufacturing costs associated with advanced planar lithography.
2Manufacturing precision
If fine patterns are formed in planar semiconductor memory devices to increase integration density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
By stacking memory layers vertically in the third dimension, the patent reduces the lateral patterning requirements. The through-holes are formed using vertical etching processes that penetrate through multiple layers, simplifying the overall manufacturing process compared to forming extremely fine lateral patterns in planar devices.
Solution Approach 2:
The memory device is divided into multiple discrete layers (first memory layer, second memory layer, etc.) separated by through-holes. Each layer can be formed and processed relatively independently, then stacked together. This segmentation allows for modular manufacturing, reducing the complexity of forming fine patterns across a continuous planar structure.
Data Source
AI summary
Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed.