3D Stacked Memory Array Layer Selection via LSMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D stacked memory arrays face limitations in selecting layers due to the limited number of threshold voltage states and string selection lines, which restricts the integrity and efficiency of memory operations.
Innovation Solution
A method for determining threshold voltages of string selection transistors using multi-level permutation (LSMP) to distribute threshold voltages evenly across semiconductor layers, allowing for the selection of layers regardless of the number of threshold voltage states and string selection lines, thereby maximizing memory integrity and minimizing the number of string selection lines required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of string selection lines is increased to select more layers, then the number of selectable layers increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the parameter of threshold voltage distribution from uniform to non-uniform (permutation-based) across string selection transistors. By programming different threshold voltage states (e.g., V0, V1, V2, V3) in a permuted pattern across SSLs and layers, the system achieves enhanced layer selection capability with the same number of SSLs, effectively resolving the contradiction between selection capability and device complexity
Solution Approach 2:
The patent introduces a new dimension of threshold voltage state distribution across the vertical stack. Instead of relying solely on the horizontal dimension (number of SSLs), it utilizes the vertical dimension (threshold voltage states of stacked transistors) to encode layer selection information. This multi-dimensional approach allows selecting up to 2^k layers with k SSLs, where each SSL can be in multiple threshold voltage states
2Adaptability or versatility
If the number of threshold voltage states is increased to improve layer selection, then the number of selectable layers increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-programming specific threshold voltage states into string selection transistors during manufacturing. The charge storage layers are programmed in advance with predetermined threshold voltage values (V0, V1, V2, V3) in a permuted pattern, so that during operation, simple voltage comparisons can determine layer selection without requiring real-time precision control of multiple threshold states
Solution Approach 2:
The patent segments the threshold voltage range into discrete, well-defined states (V0, V1, V2, V3) that are separately programmed into different string selection transistors. This segmentation allows the system to use a manageable number of distinct threshold voltage levels while achieving exponential layer selection capability through their combinatorial permutation across multiple SSLs and layers
3Device complexity
If the number of string selection transistors is reduced to minimize device complexity, then the device complexity decreases, but the number of selectable layers is limited
Solution Approach 1:
The patent exploits the vertical stacking dimension by programming threshold voltage states in the vertical direction. Each SSL contains multiple stacked transistors with different threshold voltage states, and by combining the states across the stack, the system achieves 2^k layer selection capability with only k SSLs, effectively using the vertical dimension to multiply the functional capacity of each SSL
Solution Approach 2:
The patent introduces dynamic threshold voltage distribution through permutation patterns. The threshold voltage states are not statically assigned but are dynamically permuted across SSLs and layers according to a predetermined pattern, allowing the same physical structure to support multiple layer selection configurations and maximizing the selection capability with minimal SSLs
Data Source
AI summary
This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and SSLs. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of SSLs and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process.