3D Stacked Nonvolatile Memory Read Disturb Prevention
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Solution Overview
Problem
Three-dimensional stacked nonvolatile semiconductor memories, such as BiCS-NAND flash memory, face challenges with read disturb, where the threshold voltage of non-selected memory cells in a selected block is affected due to the unique device structure, leading to variations in memory cell states.
Innovation Solution
Applying a ground potential to the channel of memory cells near the bit line side in non-selected cell units during the read operation, while applying a read potential to the selected block, and ensuring all memory cells in non-selected units are cut off from the bit line, thereby preventing channel boost and potential differences that cause read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read potential is applied to non-selected memory cells in a selected block, then reading operation can be performed, but threshold voltage variation occurs in non-selected memory cells causing read disturb
Solution Approach 1:
The memory block is divided into selected cell units and non-selected cell units. By segmenting the block and applying different potentials to different segments, the patent enables reading operations in selected units while preventing read disturb in non-selected units through the ground potential application mechanism
Solution Approach 2:
Different potential conditions are applied to different regions of the memory block. Selected cell units receive read potential for normal operation, while non-selected cell units receive ground potential to prevent threshold voltage variation, achieving local optimization of both reading capability and stability
2Quantity of substance
If three-dimensional stacked structure is used to increase memory capacity, then bit cost scalability is achieved, but read disturb problems occur due to unique device structure
Solution Approach 1:
The patent transitions from two-dimensional memory structure to three-dimensional stacked structure, enabling increased memory capacity through vertical stacking. The read disturb prevention mechanism is integrated into this 3D structure by applying ground potential to non-selected cell units at different vertical levels
Solution Approach 2:
The patent changes the potential parameter applied to non-selected memory cells from floating or high potential to ground potential (0V). This parameter change stabilizes the threshold voltage of non-selected cells in the 3D stacked structure, preventing read disturb while maintaining the capacity benefits of vertical stacking
Data Source
AI summary
In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit.