3D Stacked Nonvolatile Memory Select Gate Line Sharing
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Solution Overview
Problem
The existing three-dimensional stacked nonvolatile semiconductor memory, such as BiCS-NAND flash memory, faces challenges due to the increased area of peripheral circuits caused by the two-dimensional arrangement of select gate lines on the bit line side, which is not efficiently integrated with the three-dimensional memory cell array.
Innovation Solution
The proposed solution involves a new layout where select gate lines on the bit line side are shared between two blocks, connected to a driver in a one-to-one relation, reducing the number of transistors required for driving these lines and thus minimizing the area of the peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If select gate lines on the bit line side are disposed in one block according to the BiCS memory structure, then memory capacity is increased by stacking layers, but the area of drivers for driving the select gate lines is increased by the number of select gate lines in one block
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of select gate lines to a three-dimensional stacked structure. Multiple select gate lines are arranged vertically across different layers, allowing memory capacity to scale with the number of stacked layers while sharing driver circuits across layers, thus reducing the proportional increase in driver area.
Solution Approach 2:
The driver circuits are designed to serve multiple select gate lines across different stacked layers simultaneously. A single driver can control select gate lines in multiple layers through the vertical stacking architecture, making the driver multi-functional and reducing the total driver area required compared to having separate drivers for each select gate line.
2Volume of moving object
If the number of stacked layers is increased to exceed memory capacity limits, then memory capacity is greatly increased, but the number of transistors in peripheral circuits is increased
Solution Approach 1:
By stacking memory layers vertically in the third dimension, the patent achieves high memory capacity without proportionally increasing the planar area and transistor count in peripheral circuits. The vertical stacking allows multiple memory cells to share common peripheral circuit elements.
Solution Approach 2:
The patent merges peripheral circuit functions across multiple stacked layers, allowing shared use of driver circuits and other peripheral components. This consolidation reduces the total number of transistors required in peripheral circuits while maintaining the ability to address individual memory cells in each layer through the columnar semiconductor structure.
Data Source
AI summary
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.