3D Stacked Memory Device With Shared Vertical Wiring
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Solution Overview
Problem
Existing storage devices face challenges in achieving high storage capacity, small form factor, high reliability, low power consumption, and novel design while effectively addressing the increasing demand for data storage.
Innovation Solution
A storage device comprising N memory layers with a specific wiring configuration, including first, second, third, fourth, and fifth wirings, each connected to memory cells with transistors and capacitors, optimized for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in 3D configuration, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into N memory layers stacked in the Z direction, with each layer containing memory cells that share common bit lines and word lines. This segmentation allows independent fabrication and testing of each layer while achieving high storage capacity through vertical stacking.
Solution Approach 2:
Multiple memory layers are nested vertically with shared wiring structures. The first, second, third, and fourth wirings extend through multiple layers in the Z direction, creating a nested configuration where inner layers share outer layers' wiring infrastructure, reducing overall device complexity.
2Area of stationary object
If memory layers are stacked vertically, then area occupancy is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The memory structure transitions from planar (2D) to vertical (3D) stacking in the Z direction. Memory cells are arranged in multiple layers along the Z axis, allowing high storage capacity in a small footprint area while using precise alignment techniques for vertical wiring connections.
Solution Approach 2:
The first, second, third, and fourth wirings serve multiple functions across different memory layers. These wirings act as both bit lines and word lines for different layers, reducing the total number of wiring structures needed and simplifying manufacturing while maintaining small area occupancy.
3Device complexity
If conventional wiring configuration is used, then device complexity is low, but power consumption increases
Solution Approach 1:
Adjacent memory layers share common wiring structures (first, second, third, and fourth wirings), merging multiple wiring functions into single physical structures. This reduces the total wiring length and number of connections, thereby lowering power consumption while maintaining manageable device complexity.
Solution Approach 2:
The wiring pattern is copied and reused across multiple memory layers rather than creating unique wirings for each layer. The same wiring structures serve multiple layers, reducing overall wiring complexity and power consumption through efficient resource sharing.
Data Source
AI summary
A novel storage device is provided. A storage device in which N memory layers each including a plurality of memory cells provided in a matrix (Nis an integer greater than or equal to 2) are stacked is provided. A write bit line, a read bit line, and a selection line are provided along a stacking direction of the memory layers, and a write word line and a read word line are provided in the direction orthogonal to the stacking direction of the memory layers. The memory cell includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to the write bit line through a first conductor including a region functioning as one of a source electrode and a drain electrode. The first conductor includes a region where at least one of the top surface, a side surface, and the bottom surface of the first conductor is in contact with the write bit line.