3D Stacked Memory Vertical Interconnect via Conductive Pillars
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Solution Overview
Problem
Current 3D stacked memory devices face challenges in configuring vertical interconnects for neuromorphic and AI systems due to high process complexity and area consumption, with increased resistance in existing vertical interconnect methods, limiting the degree of integration and efficiency.
Innovation Solution
A 3D stacked memory device with a vertical interconnect structure featuring conductive via-holes filled with conductive material, where the via-holes penetrate through the cell stack, enabling effective signal transfer between memory stacks and peripheral circuits, and utilizing a conductive pillar connected to a wiring line or circuit region, with an insulating film surrounding the conductive pillar for reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is arranged between memory cell and peripheral circuit element and channel is used as vertical interconnect wiring, then electrical connection is achieved, but resistance to vertical interconnect greatly increases
Solution Approach 1:
The invention extracts the vertical interconnect function from the channel structure and creates a separate dedicated vertical interconnect structure. This separates the memory cell function from the interconnect function, allowing the channel to maintain its low-resistance properties for memory operation while the new vertical interconnect provides low-resistance wiring to peripheral circuits.
Solution Approach 2:
The invention introduces an intermediary vertical interconnect structure that mediates between the memory cell array and peripheral circuits. This intermediary structure uses conductive materials and via-holes to provide a low-resistance pathway, decoupling the high-resistance channel from direct interconnect usage.
2Device complexity
If additional insulating film stack and sidewall protective film are arranged around cell string, then vertical interconnect structure is formed, but process complexity increases
Solution Approach 1:
The cell plug structure serves multiple functions: it provides the memory cell string pathway, acts as the vertical interconnect structure, and eliminates the need for separate insulating film stacks and sidewall protective films. This multi-functionality reduces process steps while achieving the same structural goals.
Solution Approach 2:
The invention merges the cell plug formation process with the vertical interconnect structure formation. By combining these functions into a single structure, the need for additional insulating films and protective layers is eliminated, simplifying the manufacturing process.
3Ease of operation
If via-holes are formed in region not overlapping with cells, then wiring lines are created, but area consumption increases
Solution Approach 1:
The invention moves the vertical interconnect via-holes from the horizontal plane (requiring additional area) to the vertical dimension by forming them within the cell stack height. This allows wiring connections without consuming additional footprint area, as the via-holes utilize the vertical space already occupied by the memory cell structure.
Data Source
AI summary
Provided is a 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate. Vertical memory stacks and a vertical interconnect structure are provided in the cell region. The vertical interconnect structure includes: a via-hole formed along a vertical direction of the cell region; and a conductive pillar shaped by filling the via-hole with a conductive material. The vertical interconnect structure is configured to interconnect a top electrode of the vertical memory stack and a conductive region of the substrate along the vertical direction. The 3D stacked memory device has a vertical interconnect structure configured with a vertical wiring plug of a conductive material in a cell region, so that it is possible to facilitate the manufacturing process and providing a vertical interconnect between top and bottom electrodes of the stacked memory device or a peripheral circuit of the substrate.