3D Stacked MOSFET Channel Structure for Higher Logic Density
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved integration density and electrical characteristics.
Innovation Solution
A three-dimensional semiconductor device is fabricated with vertically stacked transistors, featuring a first active region on a substrate with lower source/drain regions and channel structures, and a second active region with upper source/drain regions and channel structures, enclosed by gate electrodes made of metal structures, allowing for increased integration density and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to meet demand for small pattern size and reduced design rule, then integration density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOS-FETs to three-dimensional vertically stacked transistors. Multiple channel structures are stacked in the vertical direction perpendicular to the substrate, allowing multiple transistors to occupy a smaller footprint area while maintaining adequate channel dimensions for proper operation. This dimensional change enables higher integration density without the operational degradation associated with extreme scaling of individual transistors.
Solution Approach 2:
The channel structure is divided into multiple discrete semiconductor layers stacked vertically, with each layer forming a separate channel. These segmented channels are separated by insulating layers and controlled by gate electrodes, allowing each segment to function independently while collectively achieving higher integration density in the vertical dimension.
2Area of stationary object
If vertically stacked transistors are implemented to increase integration density, then area required for logic cells reduces, but device complexity increases
Solution Approach 1:
By stacking transistors vertically in the third dimension, the patent reduces the horizontal footprint area occupied by logic cells. Multiple channels are arranged in the vertical direction, allowing more transistors to fit within the same planar area, thereby reducing the overall area required for logic cell implementation.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls multiple stacked channels simultaneously, provides electrical connection across different vertical levels, and acts as a shared control element for the entire transistor stack. This multi-functionality reduces the need for separate control structures for each channel, helping to manage device complexity.
3Quantity of substance
If multiple semiconductor layers are stacked vertically to improve integration density, then manufacturing precision requirements increase
Solution Approach 1:
sacrificial layers are deposited and patterned beforehand to define the precise positions and thicknesses of the semiconductor layers. These sacrificial structures serve as templates and alignment references during subsequent deposition and etching processes, ensuring accurate vertical stacking and registration of multiple semiconductor layers before the sacrificial layers are removed.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between adjacent semiconductor layers. These insulating layers provide physical separation, electrical isolation, and mechanical spacing that facilitates precise layer stacking. The insulating layers act as buffers that accommodate minor variations in layer thickness and position while maintaining overall structural integrity and alignment.
Data Source
AI summary
Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.