3D Stacked Multi-Core Processor Interconnects
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Solution Overview
Problem
Current multi-core processor technologies face limitations in data rate due to constraints from printed circuit board and wire bond connections, which have high parasitic capacitance and inductance, and are limited to two-dimensional communication, leading to increased costs and reduced yields.
Innovation Solution
The solution involves stacking multi-core integrated circuits with direct connections through the stack, eliminating the need for peripheral I/O connections and utilizing three-dimensional interconnects to enhance communication efficiency between processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If printed circuit board or wire bonding connections are used to connect integrated circuits, then I/O connections can be made between chips, but the minimum pitch constraint limits the number of connections and increases parasitic capacitance and inductance
Solution Approach 1:
The patent transitions from two-dimensional planar connections to three-dimensional vertical connections by stacking integrated circuits and forming connections through the stack. This dimensional change allows direct inter-chip communication without relying on peripheral I/O connections, thereby increasing the number of connections while reducing parasitic effects associated with traditional PCB and wire bond connections.
2Quantity of substance
If the size of the integrated circuit is increased to accommodate more I/O connections, then more connections can be made, but the number of dies that can be fabricated on a wafer decreases and yields are reduced
Solution Approach 1:
By stacking multiple integrated circuits vertically and forming connections through the stack, the patent enables more connections to be made without increasing the planar size of individual chips. This allows standard die sizes to be maintained, maximizing the number of dies per wafer and maintaining manufacturing yields while achieving higher connection counts through the third dimension.
3Speed
If printed circuit board and wire bond connections are used, then inter-chip communication can be established, but the large parasitics limit the maximum frequency and data rate
Solution Approach 1:
The patent extracts the communication function from the peripheral I/O connections and relocates it to direct inter-chip connections formed through the stack. This removes the harmful parasitic effects of PCB and wire bond connections from the communication path, enabling higher frequency operation and increased data rates.
Solution Approach 2:
The transition to three-dimensional vertical connections creates shorter, direct communication paths between chips, eliminating the long, high-parasitic traces required by traditional two-dimensional connections. This dimensional change directly reduces parasitic capacitance and inductance, enabling higher speed operation.
4Loss of time
If communication is constrained to two physical dimensions on a single chip, then manufacturing is simpler, but communication time increases due to longer wire lengths
Solution Approach 1:
The patent extends the communication network from two-dimensional planar routing to three-dimensional vertical routing by forming connections through the stack. This allows communicating entities to be positioned closer together in three-dimensional space, reducing wire length and communication time despite the increased structural complexity of the stacked configuration.
Data Source
AI summary
Techniques for interconnects structures for a multi-core processor including at least two multi-core integrated circuits include forming at least two multi-core integrated circuits each on a respective substrate into a stack, disposing connections through the stack between a circuit of a first one of the at least two multi-core integrated circuits and a circuit of a second, different one of the at least two multi-core integrated circuits, the integrated circuits arranged in the stack with connections of the first one connected to a receiving pad of the second one.