3D Stacked Multichip Module via Binary Etching
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Solution Overview
Problem
Conventional through-silicon via (TSV) processes for creating 3D stacked integrated circuits are costly, time-consuming, and result in lower yields due to complex handling and processing requirements, as well as manufacturing challenges with thinned wafers and high failure rates when one chip in a stack fails.
Innovation Solution
A method for creating a 3D stacked multichip module using a patterned conductor layer with aligned landing pads and electrical connectors that pass through vertical vias, allowing for efficient electrical contact between stacked die or wafers, reducing the number of processing steps and handling complexities by using a binary etching process with alternating photoresist masks to form electrical connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV process is used to create 3D stacked ICs, then electrical connections between stacked chips can be achieved, but the process requires 11 steps for each die or wafer resulting in high cost and time consumption
Solution Approach 1:
The patent segments the complex 11-step TSV process into distinct functional modules: die preparation with conductor layers, stacking arrangement, and connector formation through vertical vias. Each module can be optimized independently, reducing overall process complexity while maintaining connection reliability.
Solution Approach 2:
The patent applies preliminary action by pre-forming patterned conductor layers with electrical contact regions and landing pads on each die before stacking. This advance preparation eliminates several post-stack processing steps required in conventional TSV, reducing the total process steps from 11 to a more manageable number.
2Reliability
If conventional TSV process is used, then electrical connections can be made, but extensive handling and processing of each die results in lower yields
Solution Approach 1:
By pre-forming complete conductor patterns and landing pads on each die before stacking, the patent minimizes post-stack handling and processing. This preliminary preparation reduces the number of times dies must be handled and processed, thereby improving manufacturing yield.
Solution Approach 2:
The patent merges multiple process steps into fewer operations. For example, the formation of electrical connectors through vertical vias integrates several conventional steps (etching, deposition, patterning) into a streamlined process that reduces handling次数 and improves yield.
3Productivity
If wafer scale stacking with thinned wafers is used, then lower cost and high throughput can be achieved, but handling thinned wafers is a manufacturing challenge resulting in damaged or destroyed product
Solution Approach 1:
The patent performs preliminary strengthening by forming robust patterned conductor layers and supporting structures on each die before stacking. This preliminary reinforcement allows thinned wafers to be handled more easily during stacking without damage, combining the cost benefits of wafer thinning with improved manufacturability.
4Ease of manufacture
If die scale stacking is used, then handling is relatively easy but the cost is high
Solution Approach 1:
The patent segments the stacking process into standardized die units with pre-formed conductor patterns, allowing for systematic handling and processing. This segmentation enables efficient batch processing that reduces the per-unit cost compared to individual die handling, while maintaining the handling advantages of die-scale stacking.
Data Source
AI summary
A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.