3D Stacked Multiprocessor Cache Partitioning
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to increased cycle delays and the need for high-powered drivers, especially as operating frequency rises, in traditional 2D processor chip designs.
Innovation Solution
The implementation of a 3D stacked multiprocessor system where multiple layers of processor chips are conjoined, with processor cores sharing cache hierarchies through vertical connections, allowing for efficient communication and resource sharing across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors per chip is increased to accommodate more processors, then processing capacity is improved, but communication latency between processors increases due to longer horizontal wiring paths
Solution Approach 1:
The patent transitions from a 2-D processor chip layout to a 3-D stacked multiprocessor system. Multiple processor chips are stacked vertically and connected through short vertical interconnects, transforming the horizontal communication path into a vertical one. This dimensional change dramatically reduces the communication path length between processors on different chips, thereby reducing communication latency while maintaining high processing capacity.
2Productivity
If the chip size is increased to accommodate more processors, then processing capacity is improved, but the length of horizontal wiring between processors increases resulting in cycle delays
Solution Approach 1:
The patent stacks multiple processor chips vertically to form a 3-D structure, replacing long horizontal wiring paths with short vertical interconnects. This dimensional transformation reduces the wiring length between processors from millimeter or centimeter scale to micrometer scale, eliminating cycle delays while accommodating more processors.
Solution Approach 2:
The patent divides a large-scale processor system into multiple smaller processor chips, each containing a subset of processors. These chips are then stacked and connected vertically. This segmentation allows each chip to maintain compact wiring while the stacked configuration provides access to all processors across chips, reducing overall wiring length.
3Speed
If the operating frequency is increased to improve performance, then processing speed is improved, but cycle delay in processor communication increases
Solution Approach 1:
By stacking processor chips vertically and using short vertical interconnects, the patent reduces communication path length. This allows higher operating frequencies to be achieved because the reduced path length decreases signal propagation delay, preventing communication cycle delay from becoming the limiting factor at high frequencies.
4Reliability
If high-powered drivers are used along communication paths to maintain signal integrity, then communication reliability is improved, but power consumption increases
Solution Approach 1:
The patent replaces long horizontal communication paths with short vertical interconnects in a 3-D stacked architecture. The dramatically reduced path length reduces signal attenuation and interference, maintaining communication reliability without requiring high-powered drivers, thereby reducing power consumption.
Data Source
AI summary
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.