3D Stacked Multiprocessor System Vertical Interconnects
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to increased cycle delays and the need for high-powered drivers, especially as operating frequency rises, and integrating test infrastructure and calibration circuitry becomes costly and congested in terms of chip area and wire routing.
Innovation Solution
A 3-D stacked multiprocessor system is implemented, where multiple processor chips are integrated into a single stacked system with short vertical interconnects, allowing processors to operate independently or collaboratively, sharing resources and reducing communication latency by using vertical connections instead of horizontal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors per chip increases, then processing capability is improved, but on-chip communication becomes problematic due to increased cycle delays and wiring length
Solution Approach 1:
The patent transitions from a two-dimensional chip layout to a three-dimensional stacked architecture. Multiple processor chips are vertically stacked and interconnected through short vertical interconnects (silicon bridges) rather than relying on long horizontal wiring traces. This dimensional change reduces communication path length and cycle delay while maintaining high processing capability through parallel execution across multiple layers.
2Productivity
If the number of processors per chip increases, then processing capability is improved, but chip area and wire routing congestion increase
Solution Approach 1:
The patent utilizes vertical stacking to place multiple processor chips in the third dimension (depth) rather than spreading them out in the second dimension (plane). This allows high processing capability with many processors while keeping the footprint area small, as layers are stacked one above another sharing the same planar space.
Solution Approach 2:
Multiple processor chips are nested within each other in a stacked configuration, with each chip containing functional circuitry, calibration control circuitry, and performance instrumentation. The vertical interconnects nest between layers, creating a compact three-dimensional structure that packs high processing capability into a small volume without proportionally increasing chip area.
3Productivity
If integration density increases, then processing capability is improved, but test infrastructure and calibration circuitry become expensive and congested
Solution Approach 1:
The patent divides the chip into separate functional layers: functional circuitry layers for processing and dedicated calibration/control layers for testing and configuration. Each layer can be independently designed, fabricated, and tested. The calibration control circuitry and performance instrumentation are segregated in dedicated layers rather than being mixed with functional circuitry, reducing congestion and complexity in the test infrastructure.
Data Source
AI summary
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers.