3D Stacked Multiprocessor Vertical Interconnects
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to increased cycle delays and the need for high-powered drivers, especially as operating frequency rises, in traditional 2D processor chip designs.
Innovation Solution
The implementation of 3D stacked multiprocessor devices, where processors are connected vertically across multiple layers, allowing for shorter communication paths and enabling operation in various modes such as independent or collaborative configurations, with a mode control circuit to manage power and resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If processors are connected through long horizontal wiring in 2D chip layout, then more processors can be accommodated on chip, but communication cycle delays increase and high-powered drivers are required
Solution Approach 1:
The patent transitions from 2D planar processor arrangement to 3D stacked configuration, where processors are arranged in vertical layers. This dimensional change allows processors to be positioned closer together through vertical interconnects, significantly reducing communication distance and cycle delay while accommodating more processors per chip.
Solution Approach 2:
The chip is divided into multiple stacked layers with each layer containing processors. Vertical interconnects segment the communication paths into shorter segments between adjacent layers, reducing the overall communication path length and enabling faster data transfer between processors.
2Speed
If operating frequency is increased to improve performance, then processor speed increases, but communication cycle delay between processors worsens
Solution Approach 1:
By implementing 3D stacking, the patent creates short vertical interconnect paths between processors that do not scale with horizontal distance. This allows the communication path length to remain constant even as operating frequency increases, thereby maintaining low cycle delay while achieving high processor speeds.
3Loss of time
If 3D stacked configuration is used to reduce communication path length, then cycle delay decreases, but device complexity increases
Solution Approach 1:
The mode control circuit enables the 3D stacked processor system to operate in multiple modes (e.g., single-processor high-speed mode, dual-processor collaborative mode, independent mode). This multi-functionality allows the system to adapt to different performance requirements, managing complexity by selecting appropriate operating modes rather than always operating in the most complex configuration.
Data Source
AI summary
A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.