3D Stacked Multiprocessor Vertical Interconnects
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to increased cycle delays and the need for high-powered drivers, especially as operating frequency rises, in traditional 2D processor chip designs.
Innovation Solution
The implementation of 3D stacked multiprocessor devices, where processors are connected vertically, allowing for multiple operating modes such as resource aggregation and sharing, to enhance communication efficiency and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors per chip is increased in a 2D configuration, then processing capacity is improved, but communication cycle delay increases and power consumption increases
Solution Approach 1:
The patent transitions from a 2D processor layout to a 3D stacked configuration, placing processors on multiple layers vertically connected through short vias. This dimensional change reduces the physical distance between processors from millimeter/cm scale to micrometer scale, dramatically decreasing communication cycle delay while maintaining high processing capacity through multi-layer stacking
2Productivity
If the number of processors per chip is increased in a 2D configuration, then processing capacity is improved, but power consumption increases due to high-powered drivers
Solution Approach 1:
By stacking processors vertically in 3D, the interconnect length is reduced from long horizontal traces to short vertical vias, significantly lowering the power required for signal driving. The compact vertical architecture eliminates the need for high-powered drivers while maintaining high processing capacity through increased processor density in the vertical dimension
3Speed
If the operating frequency is increased, then processing speed is improved, but communication cycle delay increases
Solution Approach 1:
The 3D stacked architecture reduces the physical communication distance between processors from millimeter/cm scale to micrometer scale through vertical stacking. This dramatic reduction in interconnect length decreases signal propagation time, allowing processors to operate at higher frequencies without proportionally increasing communication cycle delay
Data Source
AI summary
Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.