3D Stacked NAND Flash Memory Cell Transistors
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Solution Overview
Problem
Conventional NAND flash memory devices face limitations in integration level due to leakage current and lower sensible current issues, which restrict the reduction of cell transistor size and the number of cell transistors between selection transistors, hindering further miniaturization and increased density.
Innovation Solution
A NAND flash memory device with 3-dimensionally arranged memory cells on stacked semiconductor layers, where each layer has a gate structure, bitlines, and a common source line, allowing for equipotentiality and reduced area occupation by selection transistors, enabling more efficient cell selection and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of cell transistors between selection transistors is increased to improve integration level, then the area occupied by selection transistors becomes smaller, but the read current becomes lower than the sensing circuit can detect due to increased electric resistance
Solution Approach 1:
The patent transitions from a planar 2D arrangement to a 3D stacked architecture where memory cells are arranged vertically across multiple semiconductor layers. This dimensional change allows increasing the number of cell transistors between selection transistors without proportionally increasing the planar area, thereby reducing the area occupied by selection transistors while maintaining sufficient read current through the vertical stacking configuration.
2Area of moving object
If the channel length of cell transistor is reduced to improve integration level, then the unit cell area is reduced, but the leakage current increases making it difficult to determine whether the cell transistor is programmed
Solution Approach 1:
By stacking multiple semiconductor layers vertically, the patent reduces the planar footprint of each unit cell while maintaining adequate channel dimensions that control leakage current. The vertical stacking allows the channel length to be preserved in the vertical direction rather than compressing it horizontally, thus reducing unit cell area without triggering excessive short-channel leakage effects.
3Productivity
If advanced processing technologies are developed to achieve higher integration level, then the performance and cost requirements are met, but enormous expense and longer time are required
Solution Approach 1:
The patent achieves higher integration levels by exploiting the third dimension through stacked semiconductor layers, rather than relying solely on advancing planar processing technologies. This approach increases memory density without requiring proportionally more complex fabrication processes, as the stacking architecture can be implemented using existing processing techniques applied in a vertical configuration.
Data Source
AI summary
A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.