3D Stacked Non-Volatile Memory With Separated Charge Storage
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing integration density within limited space, particularly in NAND-type array structures, which restricts further miniaturization and area utilization.
Innovation Solution
A non-volatile memory design featuring a stacked structure with shared conductive layers and vertically separated charge storage structures, combined with a vertical-type channel layer and flat-type charge storage structures, enhances integration density through a specific fabricating method involving dielectric and conductive material layers and patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in traditional planar configurations, then manufacturing processes are simpler, but the level of integration and area utilization are limited
Solution Approach 1:
The patent transitions from traditional planar (2D) memory cell arrangement to a three-dimensional stacked structure. Memory cells are arranged vertically in multiple layers, with conductive layers and charge storage structures stacked above each other. This dimensional change enables significantly higher integration density within the same footprint area, directly resolving the contradiction between integration level and manufacturing simplicity.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers and charge storage structures are stacked and integrated within a compact vertical space. Each memory cell layer contains nested components (control gates, charge storage structures, tunnel barriers) arranged in concentric or layered configurations, maximizing space utilization and achieving high integration density.
2Productivity
If charge storage structures are placed close together to increase density, then integration improves, but charge storage structure separation and data reliability deteriorate
Solution Approach 1:
The patent applies different dielectric materials with specific properties to different regions of the structure. Tunnel barrier layers use materials with specific breakdown characteristics, while charge storage structures use materials optimized for charge retention. The second dielectric layer is specifically positioned between adjacent charge storage structures to provide electrical isolation, ensuring that local material properties maintain reliability even as overall density increases.
Solution Approach 2:
The patent introduces a second dielectric layer as an intermediary substance positioned between adjacent charge storage structures in vertically stacked memory cells. This intermediate layer provides electrical isolation and prevents charge leakage between neighboring structures, enabling higher integration density while maintaining charge storage integrity and data reliability.
Data Source
AI summary
A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.