3D Stacked Package Structure With Substrate-Free Thinned Dies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages with stacked dies face challenges in achieving low-profile designs while maintaining signal processing performance due to the thickness of silicon substrates, limiting the number of dies that can be stacked.
Innovation Solution
A multi-level 3D package design with thinned dies and wafer-level fan-out assemblies, where each die is thinned to eliminate the silicon substrate, and interconnected through redistribution structures and vertical via structures, allowing for vertical stacking with reduced height and maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick semiconductor substrates are used to provide mechanical stability during die handling and assembly, then mechanical stability is improved, but package thickness increases and low-profile requirements cannot be met
Solution Approach 1:
The patent extracts and removes the thick silicon substrate from the semiconductor die, retaining only the thin active device region (several micrometers to tens of micrometers thick). This eliminates the useless substrate portion while preserving the functional signal processing layer, thereby reducing package thickness without compromising mechanical stability during assembly through alternative support structures.
Solution Approach 2:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging, arranging multiple thinned dies vertically in stacked configurations. This dimensional change allows multiple functional layers to be integrated within a compact footprint, achieving high density I/O and signal processing performance while maintaining low package profile.
2Quantity of substance
If multiple semiconductor dies are stacked vertically to achieve electronics densification, then device density is improved, but package thickness increases and low-profile requirements are not met
Solution Approach 1:
By extracting and removing the thick substrate portion from each die, the patent reduces the thickness of individual stacked components to only the necessary active device regions. This enables stacking multiple dies vertically while keeping the overall package thickness within low-profile requirements, as each die contributes minimal thickness to the total stack height.
Solution Approach 2:
The patent changes the thickness parameter of semiconductor dies from traditional hundreds of micrometers to several micrometers or tens of micrometers through substrate removal. This parameter transformation enables higher stacking densities while maintaining compatibility with low-profile package requirements for portable electronic devices.
3Quantity of substance
If wafer-level fan-out packaging is used to provide high density I/O ports, then I/O density is improved, but package size reduction is limited by die thickness
Solution Approach 1:
The patent employs three-dimensional stacked packaging architecture that vertically arranges multiple thinned dies with wafer-level fan-out interconnections. This vertical stacking in the third dimension enables high I/O port density without increasing the horizontal package footprint, as signal processing and I/O functions are distributed across multiple stacked layers rather than spread out in a single plane.
Solution Approach 2:
By removing the thick substrate and retaining only thin active device regions, the patent reduces the vertical space required for each die in the stack. This extraction enables more dies to be stacked within the same package volume, achieving high I/O density while minimizing overall package size for portable applications.
Data Source
AI summary
The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.