3D Stacked Package Via Layout for Smaller Footprint Interconnects
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Solution Overview
Problem
The increasing demand for smaller electronic devices, such as wearables and mobile products, poses a challenge for semiconductor packages due to the space-consuming nature of traditional peripheral interconnect vias in 3D stacked packages, which limit performance and capacity.
Innovation Solution
The implementation of interconnect vias directly coupled to electronics components within the package, reducing the need for peripheral interconnects and minimizing the x-y-z size of the package by stacking vias directly onto components, thereby reducing signal travel distance and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral interconnect vias (TMVs) and interposers are used to wire stacked packages, then connectivity between packages is achieved, but package size in the x/y direction increases significantly
Solution Approach 1:
The patent transitions from peripheral x/y-plane interconnects to vertical z-axis interconnects by stacking vias directly onto electronics components. This dimensional change eliminates the need for large peripheral interconnect structures, achieving connectivity through the vertical dimension rather than horizontal expansion.
Solution Approach 2:
The patent implements nested interconnect vias where second via structures are positioned directly over first via structures, creating a vertical stack configuration. This nesting approach allows multiple interconnect levels to occupy minimal footprint space while maintaining full connectivity functionality.
2Reliability
If peripheral interconnect vias are used for package connectivity, then electrical connection is established, but signal travel distance increases causing greater latency
Solution Approach 1:
The patent extracts the interconnect function from the peripheral region and relocates it directly onto the electronics component body. This extraction eliminates unnecessary signal routing through peripheral interposers and mold vias, creating direct vertical interconnect paths that minimize signal travel distance and latency.
3Ease of manufacture
If traditional peripheral interconnect structures are used, then package assembly is achieved, but thermal dissipation is increased due to longer signal paths
Solution Approach 1:
The patent reconfigures the interconnect architecture from horizontal peripheral routing to vertical stacking, changing the signal path dimension from x/y-plane to z-axis. This dimensional transformation shortens signal paths, reducing resistive heating and thermal dissipation while maintaining manufacturing feasibility through established via formation processes.
Data Source
AI summary
Electronics package device technology is disclosed. In one example, an electronics package device (202) comprises substrate (206) supporting an electronics component (208) and an interconnect via (216a-c) electrically coupled to the electronics component such that at least a portion of the electronics component is disposed between the interconnect via and the substrate. The interconnect via can be directly coupled to the electronics component such that the interconnect via and the electronics component are vertically disposed between a second electronics package device (204) and the substrate. A second electronics package device can be stacked to the first electronics package device, and can comprise similar architecture of the interconnect via attached to the electronics component as with the first electronics package. Thus, 3D package size is significantly reduced. Associated systems and processes are disclosed.